Search

Teresa M. Arroyo

Examiner (ID: 14033, Phone: (571)272-7260 , Office: P/2829 )

Most Active Art Unit
2826
Art Unit(s)
2822, 2893, 2811, 2829, 2826, 2508, 2503, 2881
Total Applications
998
Issued Applications
712
Pending Applications
86
Abandoned Applications
215

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 6114583 [patent_doc_number] => 20110074012 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-03-31 [patent_title] => 'Substrate with built-in semiconductor element, and method of fabricating substrate with built-in semiconductor element' [patent_app_type] => utility [patent_app_number] => 12/923579 [patent_app_country] => US [patent_app_date] => 2010-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 6658 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0074/20110074012.pdf [firstpage_image] =>[orig_patent_app_number] => 12923579 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/923579
Substrate with built-in semiconductor element, and method of fabricating substrate with built-in semiconductor element Sep 27, 2010 Abandoned
Array ( [id] => 8859161 [patent_doc_number] => 08461698 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-06-11 [patent_title] => 'PCB external ground plane via conductive coating' [patent_app_type] => utility [patent_app_number] => 12/892617 [patent_app_country] => US [patent_app_date] => 2010-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 3847 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12892617 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/892617
PCB external ground plane via conductive coating Sep 27, 2010 Issued
Array ( [id] => 6327450 [patent_doc_number] => 20100327293 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-12-30 [patent_title] => 'FIELD-EFFECT TRANSISTOR AND METHOD FOR FABRICATING THE SAME' [patent_app_type] => utility [patent_app_number] => 12/880704 [patent_app_country] => US [patent_app_date] => 2010-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 8182 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0327/20100327293.pdf [firstpage_image] =>[orig_patent_app_number] => 12880704 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/880704
Field-effect transistor Sep 12, 2010 Issued
Array ( [id] => 6610202 [patent_doc_number] => 20100323513 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-12-23 [patent_title] => 'FABRICATION METHOD OF SEMICONDUCTOR DEVICE HAVING CONDUCTIVE BUMPS' [patent_app_type] => utility [patent_app_number] => 12/872164 [patent_app_country] => US [patent_app_date] => 2010-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3685 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0323/20100323513.pdf [firstpage_image] =>[orig_patent_app_number] => 12872164 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/872164
Fabrication method of semiconductor device having conductive bumps Aug 30, 2010 Issued
Array ( [id] => 7787803 [patent_doc_number] => 20120049359 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-03-01 [patent_title] => 'BALL GRID ARRAY PACKAGE' [patent_app_type] => utility [patent_app_number] => 12/871452 [patent_app_country] => US [patent_app_date] => 2010-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4131 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0049/20120049359.pdf [firstpage_image] =>[orig_patent_app_number] => 12871452 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/871452
BALL GRID ARRAY PACKAGE Aug 29, 2010 Abandoned
Array ( [id] => 7787790 [patent_doc_number] => 20120049346 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-03-01 [patent_title] => 'Pillar Bumps and Process for Making Same' [patent_app_type] => utility [patent_app_number] => 12/871565 [patent_app_country] => US [patent_app_date] => 2010-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5455 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0049/20120049346.pdf [firstpage_image] =>[orig_patent_app_number] => 12871565 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/871565
Pillar bumps and process for making same Aug 29, 2010 Issued
Array ( [id] => 7787789 [patent_doc_number] => 20120049345 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-03-01 [patent_title] => 'SUBSTRATE VIAS FOR HEAT REMOVAL FROM SEMICONDUCTOR DIE' [patent_app_type] => utility [patent_app_number] => 12/869844 [patent_app_country] => US [patent_app_date] => 2010-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 8408 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0049/20120049345.pdf [firstpage_image] =>[orig_patent_app_number] => 12869844 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/869844
Substrate vias for heat removal from semiconductor die Aug 26, 2010 Issued
Array ( [id] => 6021382 [patent_doc_number] => 20110049708 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-03-03 [patent_title] => 'Semiconductor Chip Interconnection Structure and Semiconductor Package Formed Using the Same' [patent_app_type] => utility [patent_app_number] => 12/870216 [patent_app_country] => US [patent_app_date] => 2010-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3330 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0049/20110049708.pdf [firstpage_image] =>[orig_patent_app_number] => 12870216 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/870216
Semiconductor Chip Interconnection Structure and Semiconductor Package Formed Using the Same Aug 26, 2010 Abandoned
Array ( [id] => 7787816 [patent_doc_number] => 20120049372 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-03-01 [patent_title] => 'TOP TRI-METAL SYSTEM FOR SILICON POWER SEMICONDUCTOR DEVICES' [patent_app_type] => utility [patent_app_number] => 12/869940 [patent_app_country] => US [patent_app_date] => 2010-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2191 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0049/20120049372.pdf [firstpage_image] =>[orig_patent_app_number] => 12869940 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/869940
Top tri-metal system for silicon power semiconductor devices Aug 26, 2010 Issued
Array ( [id] => 5955918 [patent_doc_number] => 20110180932 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-07-28 [patent_title] => 'METHOD OF MANUFACTURING LAYERED CHIP PACKAGE' [patent_app_type] => utility [patent_app_number] => 12/869471 [patent_app_country] => US [patent_app_date] => 2010-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 32 [patent_figures_cnt] => 32 [patent_no_of_words] => 13114 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0180/20110180932.pdf [firstpage_image] =>[orig_patent_app_number] => 12869471 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/869471
Method of manufacturing layered chip package Aug 25, 2010 Issued
Array ( [id] => 6571257 [patent_doc_number] => 20100320581 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-12-23 [patent_title] => 'Semiconductor device' [patent_app_type] => utility [patent_app_number] => 12/805914 [patent_app_country] => US [patent_app_date] => 2010-08-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4016 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0320/20100320581.pdf [firstpage_image] =>[orig_patent_app_number] => 12805914 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/805914
Semiconductor device and plurality of dams Aug 23, 2010 Issued
Array ( [id] => 7716140 [patent_doc_number] => 20120006580 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-01-12 [patent_title] => 'Electrically Conductive Laminate Structures, Electrical Interconnects, And Methods Of Forming Electrical Interconnects' [patent_app_type] => utility [patent_app_number] => 12/833074 [patent_app_country] => US [patent_app_date] => 2010-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 27 [patent_no_of_words] => 4548 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0006/20120006580.pdf [firstpage_image] =>[orig_patent_app_number] => 12833074 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/833074
Electrically conductive laminate structure containing graphene region Jul 8, 2010 Issued
Array ( [id] => 6052361 [patent_doc_number] => 20110108966 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-05-12 [patent_title] => 'INTEGRATED CIRCUIT PACKAGING SYSTEM WITH CONCAVE TRENCHES AND METHOD OF MANUFACTURE THEREOF' [patent_app_type] => utility [patent_app_number] => 12/729631 [patent_app_country] => US [patent_app_date] => 2010-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3193 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0108/20110108966.pdf [firstpage_image] =>[orig_patent_app_number] => 12729631 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/729631
INTEGRATED CIRCUIT PACKAGING SYSTEM WITH CONCAVE TRENCHES AND METHOD OF MANUFACTURE THEREOF Mar 22, 2010 Abandoned
12/712825 MULTI-CHIP STACKED DEVICES Feb 24, 2010 Abandoned
Array ( [id] => 8578246 [patent_doc_number] => 08344457 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-01-01 [patent_title] => 'Insulated-gate semiconductor device with protection diode' [patent_app_type] => utility [patent_app_number] => 12/711647 [patent_app_country] => US [patent_app_date] => 2010-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 16 [patent_no_of_words] => 8609 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12711647 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/711647
Insulated-gate semiconductor device with protection diode Feb 23, 2010 Issued
Array ( [id] => 8528330 [patent_doc_number] => 08304904 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-11-06 [patent_title] => 'Semiconductor device with solder bump formed on high topography plated Cu pads' [patent_app_type] => utility [patent_app_number] => 12/700114 [patent_app_country] => US [patent_app_date] => 2010-02-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 3097 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12700114 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/700114
Semiconductor device with solder bump formed on high topography plated Cu pads Feb 3, 2010 Issued
Array ( [id] => 6519542 [patent_doc_number] => 20100123255 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-05-20 [patent_title] => 'ELECTRONIC PACKAGE STRUCTURE AND METHOD' [patent_app_type] => utility [patent_app_number] => 12/693704 [patent_app_country] => US [patent_app_date] => 2010-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 1818 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0123/20100123255.pdf [firstpage_image] =>[orig_patent_app_number] => 12693704 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/693704
Electronic package structure having conductive strip and method Jan 25, 2010 Issued
12/692270 METHOD OF MANUFACTURING LAYERED CHIP PACKAGE Jan 21, 2010 Abandoned
Array ( [id] => 8713825 [patent_doc_number] => 08399967 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-03-19 [patent_title] => 'Package structure' [patent_app_type] => utility [patent_app_number] => 12/689487 [patent_app_country] => US [patent_app_date] => 2010-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 5259 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 183 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12689487 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/689487
Package structure Jan 18, 2010 Issued
Array ( [id] => 10577015 [patent_doc_number] => 09299664 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-03-29 [patent_title] => 'Method of forming an EM protected semiconductor die' [patent_app_type] => utility [patent_app_number] => 12/689137 [patent_app_country] => US [patent_app_date] => 2010-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 19 [patent_no_of_words] => 8471 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12689137 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/689137
Method of forming an EM protected semiconductor die Jan 17, 2010 Issued
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