
Teresa M. Arroyo
Examiner (ID: 7429, Phone: (571)272-7260 , Office: P/2829 )
| Most Active Art Unit | 2826 |
| Art Unit(s) | 2893, 2826, 2503, 2811, 2829, 2822, 2881, 2508 |
| Total Applications | 972 |
| Issued Applications | 700 |
| Pending Applications | 81 |
| Abandoned Applications | 212 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 8846813
[patent_doc_number] => 08456000
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2013-06-04
[patent_title] => 'Semiconductor module and an electronic system including the same'
[patent_app_type] => utility
[patent_app_number] => 12/554173
[patent_app_country] => US
[patent_app_date] => 2009-09-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 17
[patent_figures_cnt] => 27
[patent_no_of_words] => 8654
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[patent_maintenance] => 1
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[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12554173
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/554173 | Semiconductor module and an electronic system including the same | Sep 3, 2009 | Issued |
Array
(
[id] => 5395125
[patent_doc_number] => 20090315188
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-12-24
[patent_title] => 'SILICON-ON-INSULATOR STRUCTURES FOR THROUGH VIA IN SILICON CARRIERS'
[patent_app_type] => utility
[patent_app_number] => 12/550494
[patent_app_country] => US
[patent_app_date] => 2009-08-31
[patent_effective_date] => 0000-00-00
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[pdf_file] => publications/A1/0315/20090315188.pdf
[firstpage_image] =>[orig_patent_app_number] => 12550494
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/550494 | Silicon-on-insulator structures for through via in silicon carriers | Aug 30, 2009 | Issued |
Array
(
[id] => 8738816
[patent_doc_number] => 08410589
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2013-04-02
[patent_title] => 'Lead frame, resin package, semiconductor device and resin package manufacturing method'
[patent_app_type] => utility
[patent_app_number] => 12/545176
[patent_app_country] => US
[patent_app_date] => 2009-08-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/545176 | Lead frame, resin package, semiconductor device and resin package manufacturing method | Aug 20, 2009 | Issued |
Array
(
[id] => 5300330
[patent_doc_number] => 20090294982
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-12-03
[patent_title] => 'INTERCONNECT STRUCTURES WITH TERNARY PATTERNED FEATURES GENERATED FROM TWO LITHOGRAPHIC PROCESSES'
[patent_app_type] => utility
[patent_app_number] => 12/538114
[patent_app_country] => US
[patent_app_date] => 2009-08-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
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[patent_no_of_words] => 3726
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[pdf_file] => publications/A1/0294/20090294982.pdf
[firstpage_image] =>[orig_patent_app_number] => 12538114
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/538114 | Interconnect structures with ternary patterned features generated from two lithographic processes | Aug 7, 2009 | Issued |
Array
(
[id] => 5948484
[patent_doc_number] => 20110031596
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2011-02-10
[patent_title] => 'NICKEL-TITANUM SOLDERING LAYERS IN SEMICONDUCTOR DEVICES'
[patent_app_type] => utility
[patent_app_number] => 12/535963
[patent_app_country] => US
[patent_app_date] => 2009-08-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
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[patent_no_of_claims] => 27
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[pdf_file] => publications/A1/0031/20110031596.pdf
[firstpage_image] =>[orig_patent_app_number] => 12535963
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/535963 | NICKEL-TITANUM SOLDERING LAYERS IN SEMICONDUCTOR DEVICES | Aug 4, 2009 | Abandoned |
Array
(
[id] => 9711550
[patent_doc_number] => 08836126
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2014-09-16
[patent_title] => 'Semiconductor device having insulating layers containing oxygen and a barrier layer containing manganese'
[patent_app_type] => utility
[patent_app_number] => 12/535489
[patent_app_country] => US
[patent_app_date] => 2009-08-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
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[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12535489
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/535489 | Semiconductor device having insulating layers containing oxygen and a barrier layer containing manganese | Aug 3, 2009 | Issued |
Array
(
[id] => 8329187
[patent_doc_number] => 08237285
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2012-08-07
[patent_title] => 'Semiconductor device, through hole having expansion portion and thin insulating film'
[patent_app_type] => utility
[patent_app_number] => 12/533492
[patent_app_country] => US
[patent_app_date] => 2009-07-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
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[patent_no_of_words] => 6270
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/533492 | Semiconductor device, through hole having expansion portion and thin insulating film | Jul 30, 2009 | Issued |
Array
(
[id] => 4472412
[patent_doc_number] => 07944021
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2011-05-17
[patent_title] => 'Semiconductor device with suppressed hump characteristic'
[patent_app_type] => utility
[patent_app_number] => 12/461113
[patent_app_country] => US
[patent_app_date] => 2009-07-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
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[pdf_file] => patents/07/944/07944021.pdf
[firstpage_image] =>[orig_patent_app_number] => 12461113
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/461113 | Semiconductor device with suppressed hump characteristic | Jul 30, 2009 | Issued |
Array
(
[id] => 6549901
[patent_doc_number] => 20100127391
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2010-05-27
[patent_title] => 'FIXTURE FOR SEMICONDUCTOR DEVICE AND ASSEMBLY OF SEMICONDUCTOR DEVICE'
[patent_app_type] => utility
[patent_app_number] => 12/533494
[patent_app_country] => US
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[pdf_file] => publications/A1/0127/20100127391.pdf
[firstpage_image] =>[orig_patent_app_number] => 12533494
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/533494 | Fixture for semiconductor device and assembly of semiconductor device | Jul 30, 2009 | Issued |
Array
(
[id] => 6193145
[patent_doc_number] => 20110024899
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2011-02-03
[patent_title] => 'SUBSTRATE STRUCTURE FOR CAVITY PACKAGE'
[patent_app_type] => utility
[patent_app_number] => 12/510781
[patent_app_country] => US
[patent_app_date] => 2009-07-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/510781 | SUBSTRATE STRUCTURE FOR CAVITY PACKAGE | Jul 27, 2009 | Abandoned |
Array
(
[id] => 6336867
[patent_doc_number] => 20100019380
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2010-01-28
[patent_title] => 'INTEGRATED CIRCUIT WITH MICRO-PORES CERAMIC HEAT SINK'
[patent_app_type] => utility
[patent_app_number] => 12/508227
[patent_app_country] => US
[patent_app_date] => 2009-07-23
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/508227 | INTEGRATED CIRCUIT WITH MICRO-PORES CERAMIC HEAT SINK | Jul 22, 2009 | Abandoned |
Array
(
[id] => 6272236
[patent_doc_number] => 20100117218
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[patent_issue_date] => 2010-05-13
[patent_title] => 'Stacked wafer level package and method of manufacturing the same'
[patent_app_type] => utility
[patent_app_number] => 12/458454
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Array
(
[id] => 6216167
[patent_doc_number] => 20100052190
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2010-03-04
[patent_title] => 'SEMICONDUCTOR DEVICE'
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[firstpage_image] =>[orig_patent_app_number] => 12500972
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/500972 | SEMICONDUCTOR DEVICE | Jul 9, 2009 | Abandoned |
Array
(
[id] => 8340673
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[patent_issue_date] => 2012-08-14
[patent_title] => 'Crystal structure of a solder bump of flip chip semiconductor device'
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[patent_app_number] => 12/497371
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Array
(
[id] => 8702024
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[patent_issue_date] => 2013-03-12
[patent_title] => 'Method and apparatus for placing quartz SAW devices together with clock/oscillator'
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Array
(
[id] => 6327806
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/459254 | Fermi-level unpinning structures for semiconductive devices, processes of forming same, and systems containing same | Jun 25, 2009 | Issued |
Array
(
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Array
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/486454 | Metal line of semiconductor device having a multilayer molybdenum diffusion barrier and method for forming the same | Jun 16, 2009 | Issued |
Array
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Array
(
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