
Teresa M. Arroyo
Examiner (ID: 14033, Phone: (571)272-7260 , Office: P/2829 )
| Most Active Art Unit | 2826 |
| Art Unit(s) | 2822, 2893, 2811, 2829, 2826, 2508, 2503, 2881 |
| Total Applications | 998 |
| Issued Applications | 712 |
| Pending Applications | 86 |
| Abandoned Applications | 215 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 6321335
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Array
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Array
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Array
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Array
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Array
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Array
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Array
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Array
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