
Teresa M. Arroyo
Examiner (ID: 6418, Phone: (571)272-7260 , Office: P/2829 )
| Most Active Art Unit | 2826 |
| Art Unit(s) | 2508, 2829, 2881, 2503, 2822, 2826, 2893, 2811 |
| Total Applications | 980 |
| Issued Applications | 703 |
| Pending Applications | 84 |
| Abandoned Applications | 214 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 5256750
[patent_doc_number] => 20070210382
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-09-13
[patent_title] => 'Semiconductor device and method of manufacturing the same'
[patent_app_type] => utility
[patent_app_number] => 11/703258
[patent_app_country] => US
[patent_app_date] => 2007-02-07
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[patent_drawing_sheets_cnt] => 11
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[pdf_file] => publications/A1/0210/20070210382.pdf
[firstpage_image] =>[orig_patent_app_number] => 11703258
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/703258 | MOSFET having SOI and method | Feb 6, 2007 | Issued |
Array
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[patent_issue_date] => 2007-08-09
[patent_title] => 'Semiconductor device'
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[firstpage_image] =>[orig_patent_app_number] => 11701429
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/701429 | Hetero junction semiconductor device | Feb 1, 2007 | Issued |
Array
(
[id] => 4629859
[patent_doc_number] => 08008757
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[patent_kind] => B2
[patent_issue_date] => 2011-08-30
[patent_title] => 'Resinous hollow package and producing method thereof'
[patent_app_type] => utility
[patent_app_number] => 12/162504
[patent_app_country] => US
[patent_app_date] => 2007-01-30
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/162504 | Resinous hollow package and producing method thereof | Jan 29, 2007 | Issued |
Array
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[id] => 5095653
[patent_doc_number] => 20070117262
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[patent_kind] => A1
[patent_issue_date] => 2007-05-24
[patent_title] => 'Low Profile Stacking System and Method'
[patent_app_type] => utility
[patent_app_number] => 11/626316
[patent_app_country] => US
[patent_app_date] => 2007-01-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/626316 | Low Profile Stacking System and Method | Jan 22, 2007 | Abandoned |
Array
(
[id] => 5228176
[patent_doc_number] => 20070290283
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[patent_issue_date] => 2007-12-20
[patent_title] => 'Solar cell and manufacturing method thereof'
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[pdf_file] => publications/A1/0290/20070290283.pdf
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/648375 | Solar cell, uneven surface on an insulation layer as a screen mesh pattern, and manufacturing method thereof | Dec 27, 2006 | Issued |
Array
(
[id] => 4971358
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[patent_issue_date] => 2007-05-17
[patent_title] => 'Method for producing micromechanical structures and a micromechanical structure'
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Array
(
[id] => 5574131
[patent_doc_number] => 20090141492
[patent_country] => US
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[patent_issue_date] => 2009-06-04
[patent_title] => 'LIGHT SOURCE APPARATUS, AND DISPLAY APPARATUS'
[patent_app_type] => utility
[patent_app_number] => 11/909033
[patent_app_country] => US
[patent_app_date] => 2006-12-27
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[pdf_file] => publications/A1/0141/20090141492.pdf
[firstpage_image] =>[orig_patent_app_number] => 11909033
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/909033 | Light source apparatus and display apparatus and white resist layer | Dec 26, 2006 | Issued |
Array
(
[id] => 4472409
[patent_doc_number] => 07944020
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2011-05-17
[patent_title] => 'Reverse MIM capacitor'
[patent_app_type] => utility
[patent_app_number] => 11/644535
[patent_app_country] => US
[patent_app_date] => 2006-12-22
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/07/944/07944020.pdf
[firstpage_image] =>[orig_patent_app_number] => 11644535
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/644535 | Reverse MIM capacitor | Dec 21, 2006 | Issued |
Array
(
[id] => 4986003
[patent_doc_number] => 20070152341
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2007-07-05
[patent_title] => 'Copper wiring protected by capping metal layer and method for forming for the same'
[patent_app_type] => utility
[patent_app_number] => 11/641036
[patent_app_country] => US
[patent_app_date] => 2006-12-19
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/641036 | Copper wiring protected by capping metal layer and method for forming for the same | Dec 18, 2006 | Abandoned |
Array
(
[id] => 4582735
[patent_doc_number] => 07834359
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-11-16
[patent_title] => 'Electro-optical device, transferred chip, and transfer origin substrate'
[patent_app_type] => utility
[patent_app_number] => 11/640320
[patent_app_country] => US
[patent_app_date] => 2006-12-18
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[pdf_file] => patents/07/834/07834359.pdf
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/640320 | Electro-optical device, transferred chip, and transfer origin substrate | Dec 17, 2006 | Issued |
Array
(
[id] => 4783933
[patent_doc_number] => 20080137262
[patent_country] => US
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[patent_issue_date] => 2008-06-12
[patent_title] => 'Methods and systems for capacitors'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/637283 | Methods and systems for capacitors | Dec 11, 2006 | Abandoned |
Array
(
[id] => 4829324
[patent_doc_number] => 20080128829
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[patent_title] => 'Trench MOSFET with cell layout to improve ruggedness'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/633366 | Trench MOSFET with cell layout, ruggedness, truncated corners | Dec 3, 2006 | Issued |
Array
(
[id] => 7492464
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/606895 | Semiconductor nanoparticle surface modification | Nov 30, 2006 | Issued |
Array
(
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[patent_title] => 'Layout design method of semiconductor integrated circuit having well supplied with potential different from substrate potential'
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Array
(
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Array
(
[id] => 5004791
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Array
(
[id] => 5168803
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Array
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Array
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