Search

Teresa M. Arroyo

Examiner (ID: 7429, Phone: (571)272-7260 , Office: P/2829 )

Most Active Art Unit
2826
Art Unit(s)
2893, 2826, 2503, 2811, 2829, 2822, 2881, 2508
Total Applications
972
Issued Applications
700
Pending Applications
81
Abandoned Applications
212

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3998631 [patent_doc_number] => 05892285 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-04-06 [patent_title] => 'Semiconductor connection with a top surface having an enlarged recess' [patent_app_type] => 1 [patent_app_number] => 8/801345 [patent_app_country] => US [patent_app_date] => 1997-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 3513 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/892/05892285.pdf [firstpage_image] =>[orig_patent_app_number] => 801345 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/801345
Semiconductor connection with a top surface having an enlarged recess Feb 18, 1997 Issued
Array ( [id] => 3776386 [patent_doc_number] => 05773896 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-30 [patent_title] => 'Semiconductor device having offsetchips' [patent_app_type] => 1 [patent_app_number] => 8/802025 [patent_app_country] => US [patent_app_date] => 1997-02-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 22 [patent_no_of_words] => 7797 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/773/05773896.pdf [firstpage_image] =>[orig_patent_app_number] => 802025 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/802025
Semiconductor device having offsetchips Feb 17, 1997 Issued
Array ( [id] => 3799821 [patent_doc_number] => 05780926 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-07-14 [patent_title] => 'Multichip package device having a lead frame with stacked patterned metallization layers and insulation layers' [patent_app_type] => 1 [patent_app_number] => 8/799355 [patent_app_country] => US [patent_app_date] => 1997-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 14 [patent_no_of_words] => 2166 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 199 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/780/05780926.pdf [firstpage_image] =>[orig_patent_app_number] => 799355 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/799355
Multichip package device having a lead frame with stacked patterned metallization layers and insulation layers Feb 13, 1997 Issued
Array ( [id] => 3837376 [patent_doc_number] => 05814893 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-29 [patent_title] => 'Semiconductor device having a bond pad' [patent_app_type] => 1 [patent_app_number] => 8/799925 [patent_app_country] => US [patent_app_date] => 1997-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 13 [patent_no_of_words] => 3191 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/814/05814893.pdf [firstpage_image] =>[orig_patent_app_number] => 799925 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/799925
Semiconductor device having a bond pad Feb 12, 1997 Issued
Array ( [id] => 4224900 [patent_doc_number] => 06040623 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-03-21 [patent_title] => 'Slotted lead for a semiconductor device' [patent_app_type] => 1 [patent_app_number] => 8/795056 [patent_app_country] => US [patent_app_date] => 1997-02-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 3 [patent_no_of_words] => 1521 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/040/06040623.pdf [firstpage_image] =>[orig_patent_app_number] => 795056 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/795056
Slotted lead for a semiconductor device Feb 4, 1997 Issued
Array ( [id] => 3831106 [patent_doc_number] => 05783860 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-07-21 [patent_title] => 'Heat sink bonded to a die paddle having at least one aperture' [patent_app_type] => 1 [patent_app_number] => 8/794471 [patent_app_country] => US [patent_app_date] => 1997-02-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 10 [patent_no_of_words] => 3555 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/783/05783860.pdf [firstpage_image] =>[orig_patent_app_number] => 794471 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/794471
Heat sink bonded to a die paddle having at least one aperture Feb 3, 1997 Issued
Array ( [id] => 4062337 [patent_doc_number] => 05864173 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-01-26 [patent_title] => 'Multi-layer lead frame' [patent_app_type] => 1 [patent_app_number] => 8/790274 [patent_app_country] => US [patent_app_date] => 1997-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 3360 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/864/05864173.pdf [firstpage_image] =>[orig_patent_app_number] => 790274 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/790274
Multi-layer lead frame Jan 27, 1997 Issued
Array ( [id] => 3857944 [patent_doc_number] => 05767582 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-16 [patent_title] => 'Surface conditioning insulating layer for fine line conductive pattern' [patent_app_type] => 1 [patent_app_number] => 8/789599 [patent_app_country] => US [patent_app_date] => 1997-01-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 3613 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/767/05767582.pdf [firstpage_image] =>[orig_patent_app_number] => 789599 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/789599
Surface conditioning insulating layer for fine line conductive pattern Jan 23, 1997 Issued
Array ( [id] => 3802263 [patent_doc_number] => 05828129 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-10-27 [patent_title] => 'Semiconductor memory device including a capacitor having a top portion which is a diffusion barrier' [patent_app_type] => 1 [patent_app_number] => 8/788105 [patent_app_country] => US [patent_app_date] => 1997-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 12 [patent_no_of_words] => 3139 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/828/05828129.pdf [firstpage_image] =>[orig_patent_app_number] => 788105 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/788105
Semiconductor memory device including a capacitor having a top portion which is a diffusion barrier Jan 22, 1997 Issued
Array ( [id] => 3865010 [patent_doc_number] => 05793101 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-08-11 [patent_title] => 'Package housing multiple semiconductor dies' [patent_app_type] => 1 [patent_app_number] => 8/781358 [patent_app_country] => US [patent_app_date] => 1997-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3464 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 183 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/793/05793101.pdf [firstpage_image] =>[orig_patent_app_number] => 781358 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/781358
Package housing multiple semiconductor dies Jan 20, 1997 Issued
Array ( [id] => 3972919 [patent_doc_number] => 05886415 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-03-23 [patent_title] => 'Anisotropic conductive sheet and printed circuit board' [patent_app_type] => 1 [patent_app_number] => 8/786615 [patent_app_country] => US [patent_app_date] => 1997-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 18 [patent_no_of_words] => 6332 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/886/05886415.pdf [firstpage_image] =>[orig_patent_app_number] => 786615 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/786615
Anisotropic conductive sheet and printed circuit board Jan 16, 1997 Issued
08/772033 LEADFRAME STRUCTURE WITH LOCKED INNER LEADS AND PROCESS FOR MANUFACTURING SAME Dec 18, 1996 Abandoned
Array ( [id] => 4224968 [patent_doc_number] => 06040628 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-03-21 [patent_title] => 'Interconnect structure using a combination of hard dielectric and polymer as interlayer dielectrics' [patent_app_type] => 1 [patent_app_number] => 8/769549 [patent_app_country] => US [patent_app_date] => 1996-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 4495 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/040/06040628.pdf [firstpage_image] =>[orig_patent_app_number] => 769549 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/769549
Interconnect structure using a combination of hard dielectric and polymer as interlayer dielectrics Dec 18, 1996 Issued
Array ( [id] => 4145725 [patent_doc_number] => 06060784 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-09 [patent_title] => 'Interconnection layer structure in a semiconductor integrated circuit device having macro cell regions' [patent_app_type] => 1 [patent_app_number] => 8/768577 [patent_app_country] => US [patent_app_date] => 1996-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 17 [patent_no_of_words] => 15847 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/060/06060784.pdf [firstpage_image] =>[orig_patent_app_number] => 768577 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/768577
Interconnection layer structure in a semiconductor integrated circuit device having macro cell regions Dec 17, 1996 Issued
Array ( [id] => 3896288 [patent_doc_number] => 05834832 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-11-10 [patent_title] => 'Packing structure of semiconductor packages' [patent_app_type] => 1 [patent_app_number] => 8/769799 [patent_app_country] => US [patent_app_date] => 1996-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 16 [patent_no_of_words] => 3465 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/834/05834832.pdf [firstpage_image] =>[orig_patent_app_number] => 769799 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/769799
Packing structure of semiconductor packages Dec 16, 1996 Issued
Array ( [id] => 4103287 [patent_doc_number] => 06049126 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-04-11 [patent_title] => 'Semiconductor package and amplifier employing the same' [patent_app_type] => 1 [patent_app_number] => 8/764241 [patent_app_country] => US [patent_app_date] => 1996-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 23 [patent_no_of_words] => 6621 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/049/06049126.pdf [firstpage_image] =>[orig_patent_app_number] => 764241 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/764241
Semiconductor package and amplifier employing the same Dec 15, 1996 Issued
Array ( [id] => 3909268 [patent_doc_number] => 05898215 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-04-27 [patent_title] => 'Microelectronic assembly with connection to a buried electrical element, and method for forming same' [patent_app_type] => 1 [patent_app_number] => 8/766653 [patent_app_country] => US [patent_app_date] => 1996-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 1979 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/898/05898215.pdf [firstpage_image] =>[orig_patent_app_number] => 766653 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/766653
Microelectronic assembly with connection to a buried electrical element, and method for forming same Dec 15, 1996 Issued
Array ( [id] => 3847387 [patent_doc_number] => 05708298 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-01-13 [patent_title] => 'Semiconductor memory module having double-sided stacked memory chip layout' [patent_app_type] => 1 [patent_app_number] => 8/763469 [patent_app_country] => US [patent_app_date] => 1996-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 48 [patent_no_of_words] => 10107 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 237 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/708/05708298.pdf [firstpage_image] =>[orig_patent_app_number] => 763469 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/763469
Semiconductor memory module having double-sided stacked memory chip layout Dec 9, 1996 Issued
Array ( [id] => 3880421 [patent_doc_number] => 05825087 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-10-20 [patent_title] => 'Integral mesh flat plate cooling module' [patent_app_type] => 1 [patent_app_number] => 8/758789 [patent_app_country] => US [patent_app_date] => 1996-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 3378 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/825/05825087.pdf [firstpage_image] =>[orig_patent_app_number] => 758789 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/758789
Integral mesh flat plate cooling module Dec 2, 1996 Issued
Array ( [id] => 4003106 [patent_doc_number] => 05986335 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-16 [patent_title] => 'Semiconductor device having a tapeless mounting' [patent_app_type] => 1 [patent_app_number] => 8/757777 [patent_app_country] => US [patent_app_date] => 1996-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 51 [patent_no_of_words] => 14551 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/986/05986335.pdf [firstpage_image] =>[orig_patent_app_number] => 757777 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/757777
Semiconductor device having a tapeless mounting Nov 26, 1996 Issued
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