
Terrell W. Fears
Examiner (ID: 17829)
| Most Active Art Unit | 2303 |
| Art Unit(s) | 2511, 2824, 2312, 1613, 2603, 2811, 2818, 2305, 2899, 2504, 2303 |
| Total Applications | 1964 |
| Issued Applications | 1841 |
| Pending Applications | 23 |
| Abandoned Applications | 100 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 4219418
[patent_doc_number] => 06028807
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-02-22
[patent_title] => 'Memory architecture'
[patent_app_type] => 1
[patent_app_number] => 9/110704
[patent_app_country] => US
[patent_app_date] => 1998-07-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 13
[patent_no_of_words] => 4485
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/028/06028807.pdf
[firstpage_image] =>[orig_patent_app_number] => 110704
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/110704 | Memory architecture | Jul 6, 1998 | Issued |
Array
(
[id] => 3953533
[patent_doc_number] => 05973982
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-10-26
[patent_title] => 'Pulse width amplifier circuit'
[patent_app_type] => 1
[patent_app_number] => 9/110202
[patent_app_country] => US
[patent_app_date] => 1998-07-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
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[patent_no_of_words] => 4042
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[pdf_file] => patents/05/973/05973982.pdf
[firstpage_image] =>[orig_patent_app_number] => 110202
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/110202 | Pulse width amplifier circuit | Jul 5, 1998 | Issued |
Array
(
[id] => 4064273
[patent_doc_number] => 05933372
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-08-03
[patent_title] => 'Data path for high speed high bandwidth DRAM'
[patent_app_type] => 1
[patent_app_number] => 9/109951
[patent_app_country] => US
[patent_app_date] => 1998-07-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
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[patent_no_of_words] => 3516
[patent_no_of_claims] => 32
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[patent_maintenance] => 1
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/933/05933372.pdf
[firstpage_image] =>[orig_patent_app_number] => 109951
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/109951 | Data path for high speed high bandwidth DRAM | Jul 1, 1998 | Issued |
Array
(
[id] => 4078292
[patent_doc_number] => 06009036
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-12-28
[patent_title] => 'Memory device'
[patent_app_type] => 1
[patent_app_number] => 9/101003
[patent_app_country] => US
[patent_app_date] => 1998-06-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
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[patent_no_of_words] => 5867
[patent_no_of_claims] => 8
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/009/06009036.pdf
[firstpage_image] =>[orig_patent_app_number] => 101003
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/101003 | Memory device | Jun 28, 1998 | Issued |
Array
(
[id] => 4054414
[patent_doc_number] => 05909399
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-06-01
[patent_title] => 'Non-volatile semiconductor memory device and memory system using the same'
[patent_app_type] => 1
[patent_app_number] => 9/100330
[patent_app_country] => US
[patent_app_date] => 1998-06-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 99
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[patent_no_of_words] => 28973
[patent_no_of_claims] => 22
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/909/05909399.pdf
[firstpage_image] =>[orig_patent_app_number] => 100330
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/100330 | Non-volatile semiconductor memory device and memory system using the same | Jun 18, 1998 | Issued |
Array
(
[id] => 4144036
[patent_doc_number] => 06034877
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-03-07
[patent_title] => 'Semiconductor memory array having sublithographic spacing between adjacement trenches and method for making the same'
[patent_app_type] => 1
[patent_app_number] => 9/093902
[patent_app_country] => US
[patent_app_date] => 1998-06-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 10
[patent_no_of_words] => 3674
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[patent_words_short_claim] => 63
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[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/034/06034877.pdf
[firstpage_image] =>[orig_patent_app_number] => 093902
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/093902 | Semiconductor memory array having sublithographic spacing between adjacement trenches and method for making the same | Jun 7, 1998 | Issued |
Array
(
[id] => 4330104
[patent_doc_number] => RE037059
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-02-20
[patent_title] => 'Wiring pattern of semiconductor integrated circuit device'
[patent_app_type] => 2
[patent_app_number] => 9/090401
[patent_app_country] => US
[patent_app_date] => 1998-06-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
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[patent_no_of_words] => 2505
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/RE/037/RE037059.pdf
[firstpage_image] =>[orig_patent_app_number] => 090401
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/090401 | Wiring pattern of semiconductor integrated circuit device | Jun 3, 1998 | Issued |
Array
(
[id] => 4144832
[patent_doc_number] => 06016282
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-01-18
[patent_title] => 'Clock vernier adjustment'
[patent_app_type] => 1
[patent_app_number] => 9/086401
[patent_app_country] => US
[patent_app_date] => 1998-05-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 10
[patent_no_of_words] => 6369
[patent_no_of_claims] => 62
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[patent_words_short_claim] => 83
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[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/016/06016282.pdf
[firstpage_image] =>[orig_patent_app_number] => 086401
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/086401 | Clock vernier adjustment | May 27, 1998 | Issued |
Array
(
[id] => 4231240
[patent_doc_number] => 06088258
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-07-11
[patent_title] => 'Structures for reduced topography capacitors'
[patent_app_type] => 1
[patent_app_number] => 9/086404
[patent_app_country] => US
[patent_app_date] => 1998-05-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 36
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[pdf_file] => patents/06/088/06088258.pdf
[firstpage_image] =>[orig_patent_app_number] => 086404
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/086404 | Structures for reduced topography capacitors | May 27, 1998 | Issued |
| 09/085705 | METHOD FOR PROGRAMMING FLASH ELECTRICALLY ERASABLE PROGRAMMABLE READ-ONLY MEMORY | May 26, 1998 | Issued |
| 09/073104 | ELECTRICALLY ERASABLE AND PROGRAMMABLE READ-ONLY MEMORY HAVING A SMALL UNIT FOR PROGRAM AND ERASE | May 4, 1998 | Issued |
Array
(
[id] => 4185035
[patent_doc_number] => RE036842
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-08-29
[patent_title] => 'Semiconductor memory device for maintaining level of signal line'
[patent_app_type] => 2
[patent_app_number] => 9/070016
[patent_app_country] => US
[patent_app_date] => 1998-04-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 23
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[patent_no_of_words] => 16869
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[pdf_file] => patents/RE/036/RE036842.pdf
[firstpage_image] =>[orig_patent_app_number] => 070016
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/070016 | Semiconductor memory device for maintaining level of signal line | Apr 29, 1998 | Issued |
Array
(
[id] => 4027107
[patent_doc_number] => 05907503
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-05-25
[patent_title] => 'Vertical bipolar SRAM cell, array and system, and a method for making the cell and the array'
[patent_app_type] => 1
[patent_app_number] => 9/070706
[patent_app_country] => US
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[pdf_file] => patents/05/907/05907503.pdf
[firstpage_image] =>[orig_patent_app_number] => 070706
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/070706 | Vertical bipolar SRAM cell, array and system, and a method for making the cell and the array | Apr 29, 1998 | Issued |
Array
(
[id] => 4064218
[patent_doc_number] => 05933368
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-08-03
[patent_title] => 'Flash memory mass storage system'
[patent_app_type] => 1
[patent_app_number] => 9/067449
[patent_app_country] => US
[patent_app_date] => 1998-04-27
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[pdf_file] => patents/05/933/05933368.pdf
[firstpage_image] =>[orig_patent_app_number] => 067449
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/067449 | Flash memory mass storage system | Apr 26, 1998 | Issued |
Array
(
[id] => 3993967
[patent_doc_number] => 05910925
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-06-08
[patent_title] => 'EEPROM with split gate source side injection'
[patent_app_type] => 1
[patent_app_number] => 9/065409
[patent_app_country] => US
[patent_app_date] => 1998-04-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/910/05910925.pdf
[firstpage_image] =>[orig_patent_app_number] => 065409
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/065409 | EEPROM with split gate source side injection | Apr 22, 1998 | Issued |
| 09/062008 | TWO TRANSISTOR FLASH EEPROM CELL AND METHOD OF OPERATING SAME | Apr 15, 1998 | Issued |
| 09/060400 | APPARATUS AND METHOD FOR TESTING A MEMORY | Apr 13, 1998 | Issued |
Array
(
[id] => 3963767
[patent_doc_number] => 05978259
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-11-02
[patent_title] => 'Semiconductor memory device'
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[patent_app_number] => 9/057604
[patent_app_country] => US
[patent_app_date] => 1998-04-09
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/05/978/05978259.pdf
[firstpage_image] =>[orig_patent_app_number] => 057604
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/057604 | Semiconductor memory device | Apr 8, 1998 | Issued |
Array
(
[id] => 4010578
[patent_doc_number] => 05923591
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[patent_kind] => NA
[patent_issue_date] => 1999-07-13
[patent_title] => 'Memory circuit'
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[patent_app_number] => 9/055327
[patent_app_country] => US
[patent_app_date] => 1998-04-05
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[pdf_file] => patents/05/923/05923591.pdf
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/055327 | Memory circuit | Apr 4, 1998 | Issued |
Array
(
[id] => 4194095
[patent_doc_number] => 06021083
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[patent_kind] => NA
[patent_issue_date] => 2000-02-01
[patent_title] => 'Block decoded wordline driver with positive and negative voltage modes'
[patent_app_type] => 1
[patent_app_number] => 9/051005
[patent_app_country] => US
[patent_app_date] => 1998-03-30
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[pdf_file] => patents/06/021/06021083.pdf
[firstpage_image] =>[orig_patent_app_number] => 051005
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/051005 | Block decoded wordline driver with positive and negative voltage modes | Mar 29, 1998 | Issued |