Search

Terrell W. Fears

Examiner (ID: 17829)

Most Active Art Unit
2303
Art Unit(s)
2511, 2824, 2312, 1613, 2603, 2811, 2818, 2305, 2899, 2504, 2303
Total Applications
1964
Issued Applications
1841
Pending Applications
23
Abandoned Applications
100

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3997937 [patent_doc_number] => 05959881 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-28 [patent_title] => 'Programmable logic device including configuration data or user data memory slices' [patent_app_type] => 1 [patent_app_number] => 9/001156 [patent_app_country] => US [patent_app_date] => 1997-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 61 [patent_figures_cnt] => 81 [patent_no_of_words] => 25741 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/959/05959881.pdf [firstpage_image] =>[orig_patent_app_number] => 001156 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/001156
Programmable logic device including configuration data or user data memory slices Dec 29, 1997 Issued
Array ( [id] => 3957000 [patent_doc_number] => 05982657 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-09 [patent_title] => 'Circuit and method for biasing the charging capacitor of a semiconductor memory array' [patent_app_type] => 1 [patent_app_number] => 8/993804 [patent_app_country] => US [patent_app_date] => 1997-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 2579 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/982/05982657.pdf [firstpage_image] =>[orig_patent_app_number] => 993804 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/993804
Circuit and method for biasing the charging capacitor of a semiconductor memory array Dec 17, 1997 Issued
Array ( [id] => 4027436 [patent_doc_number] => 05881017 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-03-09 [patent_title] => 'Synchronous semiconductor memory device allowing fast operation in either of prefetch operation and full page mode operation' [patent_app_type] => 1 [patent_app_number] => 8/992901 [patent_app_country] => US [patent_app_date] => 1997-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 30 [patent_no_of_words] => 14739 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 284 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/881/05881017.pdf [firstpage_image] =>[orig_patent_app_number] => 992901 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/992901
Synchronous semiconductor memory device allowing fast operation in either of prefetch operation and full page mode operation Dec 17, 1997 Issued
Array ( [id] => 4010435 [patent_doc_number] => 05923581 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-07-13 [patent_title] => 'Information recording medium, reading apparatus for said medium and processes for implementing said apparatus' [patent_app_type] => 1 [patent_app_number] => 8/991001 [patent_app_country] => US [patent_app_date] => 1997-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 2978 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/923/05923581.pdf [firstpage_image] =>[orig_patent_app_number] => 991001 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/991001
Information recording medium, reading apparatus for said medium and processes for implementing said apparatus Dec 14, 1997 Issued
90/004858 SEQUENTIALLY CLOCKED SUBSTRATE BIAS GENERATOR FOR DYNAMIC MEMORY Dec 4, 1997 Issued
Array ( [id] => 4417426 [patent_doc_number] => 06172910 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-09 [patent_title] => 'Test cell for analyzing a property of the flash EEPROM cell and method of analyzing a property of the flash EEPROM cell using the same' [patent_app_type] => 1 [patent_app_number] => 8/984902 [patent_app_country] => US [patent_app_date] => 1997-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 3111 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/172/06172910.pdf [firstpage_image] =>[orig_patent_app_number] => 984902 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/984902
Test cell for analyzing a property of the flash EEPROM cell and method of analyzing a property of the flash EEPROM cell using the same Dec 3, 1997 Issued
Array ( [id] => 3969874 [patent_doc_number] => 05936876 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-10 [patent_title] => 'Semiconductor integrated circuit core probing for failure analysis' [patent_app_type] => 1 [patent_app_number] => 8/984003 [patent_app_country] => US [patent_app_date] => 1997-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 3919 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/936/05936876.pdf [firstpage_image] =>[orig_patent_app_number] => 984003 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/984003
Semiconductor integrated circuit core probing for failure analysis Dec 2, 1997 Issued
Array ( [id] => 4086433 [patent_doc_number] => 05966341 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-10-12 [patent_title] => 'Semiconductor memory' [patent_app_type] => 1 [patent_app_number] => 8/982398 [patent_app_country] => US [patent_app_date] => 1997-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 32 [patent_no_of_words] => 18434 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 357 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/966/05966341.pdf [firstpage_image] =>[orig_patent_app_number] => 982398 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/982398
Semiconductor memory Dec 1, 1997 Issued
Array ( [id] => 1437660 [patent_doc_number] => 06356475 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-03-12 [patent_title] => 'Ferroelectric memory and method of reading out data from the ferroelectric memory' [patent_app_type] => B1 [patent_app_number] => 08/977664 [patent_app_country] => US [patent_app_date] => 1997-11-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 72 [patent_figures_cnt] => 122 [patent_no_of_words] => 61481 [patent_no_of_claims] => 60 [patent_no_of_ind_claims] => 13 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/356/06356475.pdf [firstpage_image] =>[orig_patent_app_number] => 08977664 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/977664
Ferroelectric memory and method of reading out data from the ferroelectric memory Nov 23, 1997 Issued
Array ( [id] => 3925123 [patent_doc_number] => 06002614 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-12-14 [patent_title] => 'Memory apparatus including programmable non-volatile multi-bit memory cell, and apparatus and method for demarcating memory states of the cell' [patent_app_type] => 1 [patent_app_number] => 8/975919 [patent_app_country] => US [patent_app_date] => 1997-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 26 [patent_no_of_words] => 11389 [patent_no_of_claims] => 77 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/002/06002614.pdf [firstpage_image] =>[orig_patent_app_number] => 975919 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/975919
Memory apparatus including programmable non-volatile multi-bit memory cell, and apparatus and method for demarcating memory states of the cell Nov 20, 1997 Issued
Array ( [id] => 3802690 [patent_doc_number] => 05841721 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-11-24 [patent_title] => 'Multi-block erase and verification circuit in a nonvolatile semiconductor memory device and a method thereof' [patent_app_type] => 1 [patent_app_number] => 8/975704 [patent_app_country] => US [patent_app_date] => 1997-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 21 [patent_no_of_words] => 13306 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 231 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/841/05841721.pdf [firstpage_image] =>[orig_patent_app_number] => 975704 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/975704
Multi-block erase and verification circuit in a nonvolatile semiconductor memory device and a method thereof Nov 20, 1997 Issued
Array ( [id] => 3889657 [patent_doc_number] => 05825708 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-10-20 [patent_title] => 'Control system for allowing multiple chips of a disk drive to safely assert and de-assert a reset signal on a reset line' [patent_app_type] => 1 [patent_app_number] => 8/972405 [patent_app_country] => US [patent_app_date] => 1997-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 6141 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/825/05825708.pdf [firstpage_image] =>[orig_patent_app_number] => 972405 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/972405
Control system for allowing multiple chips of a disk drive to safely assert and de-assert a reset signal on a reset line Nov 17, 1997 Issued
Array ( [id] => 4073200 [patent_doc_number] => 05896321 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-04-20 [patent_title] => 'Text completion system for a miniature computer' [patent_app_type] => 1 [patent_app_number] => 8/970310 [patent_app_country] => US [patent_app_date] => 1997-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 16162 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/896/05896321.pdf [firstpage_image] =>[orig_patent_app_number] => 970310 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/970310
Text completion system for a miniature computer Nov 13, 1997 Issued
Array ( [id] => 4038371 [patent_doc_number] => 05903488 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-05-11 [patent_title] => 'Semiconductor memory with improved word line structure' [patent_app_type] => 1 [patent_app_number] => 8/967710 [patent_app_country] => US [patent_app_date] => 1997-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 27 [patent_no_of_words] => 7739 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/903/05903488.pdf [firstpage_image] =>[orig_patent_app_number] => 967710 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/967710
Semiconductor memory with improved word line structure Nov 9, 1997 Issued
Array ( [id] => 4209149 [patent_doc_number] => RE036732 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-06-13 [patent_title] => 'Non-volatile memory device with a sense amplifier capable of copying back' [patent_app_type] => 2 [patent_app_number] => 8/965426 [patent_app_country] => US [patent_app_date] => 1997-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 21 [patent_no_of_words] => 6330 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/RE/036/RE036732.pdf [firstpage_image] =>[orig_patent_app_number] => 965426 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/965426
Non-volatile memory device with a sense amplifier capable of copying back Nov 5, 1997 Issued
Array ( [id] => 4027372 [patent_doc_number] => 05907519 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-05-25 [patent_title] => 'Write driver circuit with write-per-bit data masking function' [patent_app_type] => 1 [patent_app_number] => 8/963804 [patent_app_country] => US [patent_app_date] => 1997-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2372 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/907/05907519.pdf [firstpage_image] =>[orig_patent_app_number] => 963804 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/963804
Write driver circuit with write-per-bit data masking function Nov 3, 1997 Issued
Array ( [id] => 3998351 [patent_doc_number] => 05959905 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-28 [patent_title] => 'Cell-based integrated circuit design repair using gate array repair cells' [patent_app_type] => 1 [patent_app_number] => 8/962608 [patent_app_country] => US [patent_app_date] => 1997-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 2333 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/959/05959905.pdf [firstpage_image] =>[orig_patent_app_number] => 962608 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/962608
Cell-based integrated circuit design repair using gate array repair cells Oct 30, 1997 Issued
Array ( [id] => 3986343 [patent_doc_number] => 05905668 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-05-18 [patent_title] => 'Content addressable memory device' [patent_app_type] => 1 [patent_app_number] => 8/958402 [patent_app_country] => US [patent_app_date] => 1997-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5432 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/905/05905668.pdf [firstpage_image] =>[orig_patent_app_number] => 958402 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/958402
Content addressable memory device Oct 28, 1997 Issued
Array ( [id] => 3950852 [patent_doc_number] => 05930198 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-07-27 [patent_title] => 'Memory having a plurality of external clock signal inputs' [patent_app_type] => 1 [patent_app_number] => 8/960405 [patent_app_country] => US [patent_app_date] => 1997-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4486 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/930/05930198.pdf [firstpage_image] =>[orig_patent_app_number] => 960405 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/960405
Memory having a plurality of external clock signal inputs Oct 28, 1997 Issued
Array ( [id] => 4073288 [patent_doc_number] => 05896327 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-04-20 [patent_title] => 'Memory redundancy circuit for high density memory with extra row and column for failed address storage' [patent_app_type] => 1 [patent_app_number] => 8/958101 [patent_app_country] => US [patent_app_date] => 1997-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 6832 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 246 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/896/05896327.pdf [firstpage_image] =>[orig_patent_app_number] => 958101 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/958101
Memory redundancy circuit for high density memory with extra row and column for failed address storage Oct 26, 1997 Issued
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