Search

Terrell W. Fears

Examiner (ID: 19115)

Most Active Art Unit
2303
Art Unit(s)
2312, 2811, 2511, 2303, 2305, 2824, 1613, 2818, 2504, 2603, 2899
Total Applications
1964
Issued Applications
1841
Pending Applications
23
Abandoned Applications
100

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4011752 [patent_doc_number] => 05986916 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-16 [patent_title] => 'On-chip program voltage generator for antifuse repair' [patent_app_type] => 1 [patent_app_number] => 8/915341 [patent_app_country] => US [patent_app_date] => 1997-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 1293 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 43 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/986/05986916.pdf [firstpage_image] =>[orig_patent_app_number] => 915341 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/915341
On-chip program voltage generator for antifuse repair Aug 19, 1997 Issued
Array ( [id] => 3948618 [patent_doc_number] => 05872735 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-02-16 [patent_title] => 'Electrically alterable non-volatile memory with N-bits per cell' [patent_app_type] => 1 [patent_app_number] => 8/911731 [patent_app_country] => US [patent_app_date] => 1997-08-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 7040 [patent_no_of_claims] => 48 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/872/05872735.pdf [firstpage_image] =>[orig_patent_app_number] => 911731 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/911731
Electrically alterable non-volatile memory with N-bits per cell Aug 14, 1997 Issued
Array ( [id] => 4251433 [patent_doc_number] => 06091618 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-07-18 [patent_title] => 'Method and circuitry for storing discrete amounts of charge in a single memory element' [patent_app_type] => 1 [patent_app_number] => 8/910761 [patent_app_country] => US [patent_app_date] => 1997-08-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 7139 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/091/06091618.pdf [firstpage_image] =>[orig_patent_app_number] => 910761 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/910761
Method and circuitry for storing discrete amounts of charge in a single memory element Aug 12, 1997 Issued
90/004717 MEMORY SYSTEM USING PIPELINE CIRCUITRY FOR IMPROVED SYSTEM Aug 7, 1997 Issued
Array ( [id] => 3883037 [patent_doc_number] => 05838626 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-11-17 [patent_title] => 'Non-volatile memory' [patent_app_type] => 1 [patent_app_number] => 8/908708 [patent_app_country] => US [patent_app_date] => 1997-08-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4491 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/838/05838626.pdf [firstpage_image] =>[orig_patent_app_number] => 908708 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/908708
Non-volatile memory Aug 7, 1997 Issued
Array ( [id] => 3807607 [patent_doc_number] => 05781467 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-07-14 [patent_title] => 'Decoding method for ROM matrix having a silicon controlled rectifier structure' [patent_app_type] => 1 [patent_app_number] => 8/907004 [patent_app_country] => US [patent_app_date] => 1997-08-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 13 [patent_no_of_words] => 3823 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 264 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/781/05781467.pdf [firstpage_image] =>[orig_patent_app_number] => 907004 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/907004
Decoding method for ROM matrix having a silicon controlled rectifier structure Aug 5, 1997 Issued
Array ( [id] => 4054626 [patent_doc_number] => 05912854 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-06-15 [patent_title] => 'Data processing system arranged for operating synchronously with a high speed memory' [patent_app_type] => 1 [patent_app_number] => 8/905751 [patent_app_country] => US [patent_app_date] => 1997-08-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 24 [patent_no_of_words] => 8771 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/912/05912854.pdf [firstpage_image] =>[orig_patent_app_number] => 905751 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/905751
Data processing system arranged for operating synchronously with a high speed memory Aug 3, 1997 Issued
08/904405 METHOD AND SYSTEM FOR STORING AND RETRIEVING DATA Jul 30, 1997 Abandoned
Array ( [id] => 3915278 [patent_doc_number] => 05898621 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-04-27 [patent_title] => 'Batch erasable single chip nonvolatile memory device and erasing method therefor' [patent_app_type] => 1 [patent_app_number] => 8/904276 [patent_app_country] => US [patent_app_date] => 1997-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 19 [patent_no_of_words] => 9599 [patent_no_of_claims] => 50 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/898/05898621.pdf [firstpage_image] =>[orig_patent_app_number] => 904276 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/904276
Batch erasable single chip nonvolatile memory device and erasing method therefor Jul 30, 1997 Issued
Array ( [id] => 3837773 [patent_doc_number] => 05784327 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-07-21 [patent_title] => 'Memory cell array selection circuits' [patent_app_type] => 1 [patent_app_number] => 8/903047 [patent_app_country] => US [patent_app_date] => 1997-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 36 [patent_figures_cnt] => 44 [patent_no_of_words] => 37152 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 320 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/784/05784327.pdf [firstpage_image] =>[orig_patent_app_number] => 903047 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/903047
Memory cell array selection circuits Jul 29, 1997 Issued
Array ( [id] => 3756548 [patent_doc_number] => 05801981 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-01 [patent_title] => 'Serial access memory with reduced loop-line delay' [patent_app_type] => 1 [patent_app_number] => 8/901680 [patent_app_country] => US [patent_app_date] => 1997-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 14 [patent_no_of_words] => 4850 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/801/05801981.pdf [firstpage_image] =>[orig_patent_app_number] => 901680 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/901680
Serial access memory with reduced loop-line delay Jul 27, 1997 Issued
Array ( [id] => 3830708 [patent_doc_number] => 05790469 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-08-04 [patent_title] => 'Programmable voltage supply circuitry' [patent_app_type] => 1 [patent_app_number] => 8/899714 [patent_app_country] => US [patent_app_date] => 1997-07-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2404 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/790/05790469.pdf [firstpage_image] =>[orig_patent_app_number] => 899714 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/899714
Programmable voltage supply circuitry Jul 22, 1997 Issued
Array ( [id] => 3853373 [patent_doc_number] => 05847987 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-12-08 [patent_title] => 'Low currency redundancy anti-fuse method and apparatus' [patent_app_type] => 1 [patent_app_number] => 8/896701 [patent_app_country] => US [patent_app_date] => 1997-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 5516 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 274 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/847/05847987.pdf [firstpage_image] =>[orig_patent_app_number] => 896701 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/896701
Low currency redundancy anti-fuse method and apparatus Jul 17, 1997 Issued
Array ( [id] => 4034488 [patent_doc_number] => 05926419 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-07-20 [patent_title] => 'Silicon layer arrangement for last mask programmability' [patent_app_type] => 1 [patent_app_number] => 8/892957 [patent_app_country] => US [patent_app_date] => 1997-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4307 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/926/05926419.pdf [firstpage_image] =>[orig_patent_app_number] => 892957 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/892957
Silicon layer arrangement for last mask programmability Jul 14, 1997 Issued
Array ( [id] => 3853728 [patent_doc_number] => 05848010 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-12-08 [patent_title] => 'Circuit and method for antifuse stress test' [patent_app_type] => 1 [patent_app_number] => 8/892605 [patent_app_country] => US [patent_app_date] => 1997-07-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 4200 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 43 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/848/05848010.pdf [firstpage_image] =>[orig_patent_app_number] => 892605 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/892605
Circuit and method for antifuse stress test Jul 13, 1997 Issued
Array ( [id] => 4176497 [patent_doc_number] => RE036490 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-01-11 [patent_title] => 'Power and signal line bussing method for memory devices' [patent_app_type] => 2 [patent_app_number] => 8/886107 [patent_app_country] => US [patent_app_date] => 1997-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 4 [patent_no_of_words] => 963 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/RE/036/RE036490.pdf [firstpage_image] =>[orig_patent_app_number] => 886107 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/886107
Power and signal line bussing method for memory devices Jun 29, 1997 Issued
Array ( [id] => 4011826 [patent_doc_number] => 05986921 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-16 [patent_title] => 'Clock circuit for reading a multilevel non volatile memory cells device' [patent_app_type] => 1 [patent_app_number] => 8/883822 [patent_app_country] => US [patent_app_date] => 1997-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 3010 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/986/05986921.pdf [firstpage_image] =>[orig_patent_app_number] => 883822 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/883822
Clock circuit for reading a multilevel non volatile memory cells device Jun 26, 1997 Issued
Array ( [id] => 4230738 [patent_doc_number] => 06041010 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-03-21 [patent_title] => 'Graphics controller integrated circuit without memory interface pins and associated power dissipation' [patent_app_type] => 1 [patent_app_number] => 8/883538 [patent_app_country] => US [patent_app_date] => 1997-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 14 [patent_no_of_words] => 7434 [patent_no_of_claims] => 47 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/041/06041010.pdf [firstpage_image] =>[orig_patent_app_number] => 883538 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/883538
Graphics controller integrated circuit without memory interface pins and associated power dissipation Jun 25, 1997 Issued
Array ( [id] => 3789364 [patent_doc_number] => 05808950 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-15 [patent_title] => 'Semiconductor storage device' [patent_app_type] => 1 [patent_app_number] => 8/881303 [patent_app_country] => US [patent_app_date] => 1997-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4396 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/808/05808950.pdf [firstpage_image] =>[orig_patent_app_number] => 881303 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/881303
Semiconductor storage device Jun 23, 1997 Issued
Array ( [id] => 3969846 [patent_doc_number] => 05936874 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-10 [patent_title] => 'High density semiconductor memory and method of making' [patent_app_type] => 1 [patent_app_number] => 8/879207 [patent_app_country] => US [patent_app_date] => 1997-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 26 [patent_no_of_words] => 4266 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/936/05936874.pdf [firstpage_image] =>[orig_patent_app_number] => 879207 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/879207
High density semiconductor memory and method of making Jun 18, 1997 Issued
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