
Terrell W. Fears
Examiner (ID: 17829)
| Most Active Art Unit | 2303 |
| Art Unit(s) | 2511, 2824, 2312, 1613, 2603, 2811, 2818, 2305, 2899, 2504, 2303 |
| Total Applications | 1964 |
| Issued Applications | 1841 |
| Pending Applications | 23 |
| Abandoned Applications | 100 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 4318100
[patent_doc_number] => 06252804
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-06-26
[patent_title] => 'Semiconductor integrated circuit, and method of controlling same'
[patent_app_type] => 1
[patent_app_number] => 9/629619
[patent_app_country] => US
[patent_app_date] => 2000-07-31
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[patent_no_of_words] => 12510
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[pdf_file] => patents/06/252/06252804.pdf
[firstpage_image] =>[orig_patent_app_number] => 629619
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/629619 | Semiconductor integrated circuit, and method of controlling same | Jul 30, 2000 | Issued |
Array
(
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[patent_doc_number] => 06320794
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[patent_kind] => NA
[patent_issue_date] => 2001-11-20
[patent_title] => 'Late-write type semiconductor memory device with multi-channel data output multiplexer'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/614823 | Late-write type semiconductor memory device with multi-channel data output multiplexer | Jul 11, 2000 | Issued |
Array
(
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[patent_issue_date] => 2001-10-16
[patent_title] => 'Method and apparatus for storing data using spin-polarized electrons'
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Array
(
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[patent_doc_number] => 06392936
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[patent_kind] => B1
[patent_issue_date] => 2002-05-21
[patent_title] => 'Method and apparatus for generating from a single supply line voltages internal to a flash memory with reduced settling times'
[patent_app_type] => B1
[patent_app_number] => 09/608239
[patent_app_country] => US
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Array
(
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[patent_doc_number] => 06314050
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[patent_kind] => NA
[patent_issue_date] => 2001-11-06
[patent_title] => 'Data strobe buffer in SDRAM'
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Array
(
[id] => 4331378
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[patent_issue_date] => 2001-06-19
[patent_title] => 'Fast full signal differential output path circuit for high-speed memory'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/605221 | Fast full signal differential output path circuit for high-speed memory | Jun 27, 2000 | Issued |
Array
(
[id] => 4317620
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Array
(
[id] => 4373804
[patent_doc_number] => 06256223
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[patent_kind] => NA
[patent_issue_date] => 2001-07-03
[patent_title] => 'Current-induced magnetic switching device and memory including the same'
[patent_app_type] => 1
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[pdf_file] => patents/06/256/06256223.pdf
[firstpage_image] =>[orig_patent_app_number] => 597223
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/597223 | Current-induced magnetic switching device and memory including the same | Jun 19, 2000 | Issued |
Array
(
[id] => 4273174
[patent_doc_number] => 06259623
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-07-10
[patent_title] => 'Static random access memory (SRAM) circuit'
[patent_app_type] => 1
[patent_app_number] => 9/595619
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/595619 | Static random access memory (SRAM) circuit | Jun 15, 2000 | Issued |
Array
(
[id] => 1437682
[patent_doc_number] => 06356486
[patent_country] => US
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[patent_issue_date] => 2002-03-12
[patent_title] => 'Electrically alterable non-volatile memory with n-bits per cell'
[patent_app_type] => B1
[patent_app_number] => 09/586967
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/586967 | Electrically alterable non-volatile memory with n-bits per cell | Jun 4, 2000 | Issued |
Array
(
[id] => 4273540
[patent_doc_number] => 06259647
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[patent_title] => 'Synchronous semiconductor memory device allowing easy and fast test'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/587271 | Synchronous semiconductor memory device allowing easy and fast test | Jun 4, 2000 | Issued |
Array
(
[id] => 4393856
[patent_doc_number] => 06295234
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[patent_issue_date] => 2001-09-25
[patent_title] => 'Sequencer based serial port'
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Array
(
[id] => 4351564
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[patent_issue_date] => 2001-10-16
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Array
(
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Array
(
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Array
(
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Array
(
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Array
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Array
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Array
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/545615 | Apparatus and method for maintaining bit line charge state during a read operation | Apr 5, 2000 | Issued |