Terrell W. Fears

Array ( [id] => 1496424 [patent_doc_number] => 06343034 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-01-29 [patent_title] => 'Electrically alterable non-volatile memory with n-bits per cell' [patent_app_type] => B2 [patent_app_number] => 09/493140 [patent_app_country] => US [patent_app_date] => 2000-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 7259 [patent_no_of_claims] => 56 [patent_no_of_ind_claims] => 16 [patent_words_short_claim] => 1012 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/343/06343034.pdf [firstpage_image] =>[orig_patent_app_number] => 09493140 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4368222 [patent_doc_number] => 06201761 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-13 [patent_title] => 'Field effect transistor with controlled body bias' [patent_app_type] => 1 [patent_app_number] => 9/491823 [patent_app_country] => US [patent_app_date] => 2000-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 4454 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/201/06201761.pdf [firstpage_image] =>[orig_patent_app_number] => 491823 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4309297 [patent_doc_number] => 06181620 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-30 [patent_title] => 'Semiconductor storage device' [patent_app_type] => 1 [patent_app_number] => 9/484023 [patent_app_country] => US [patent_app_date] => 2000-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6477 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 200 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/181/06181620.pdf [firstpage_image] =>[orig_patent_app_number] => 484023 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4309325 [patent_doc_number] => 06181622 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-30 [patent_title] => 'Semiconductor memory' [patent_app_type] => 1 [patent_app_number] => 9/482921 [patent_app_country] => US [patent_app_date] => 2000-01-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 28 [patent_no_of_words] => 23138 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/181/06181622.pdf [firstpage_image] =>[orig_patent_app_number] => 482921 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4262724 [patent_doc_number] => 06222766 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-24 [patent_title] => 'EEPROM memory cell and method of fabricating the same' [patent_app_type] => 1 [patent_app_number] => 9/481915 [patent_app_country] => US [patent_app_date] => 2000-01-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 15 [patent_no_of_words] => 3447 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/222/06222766.pdf [firstpage_image] =>[orig_patent_app_number] => 481915 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1570326 [patent_doc_number] => 06377484 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-23 [patent_title] => 'Embedded electrically programmable read only memory devices' [patent_app_type] => B1 [patent_app_number] => 09/480915 [patent_app_country] => US [patent_app_date] => 2000-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 15 [patent_no_of_words] => 4907 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 49 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/377/06377484.pdf [firstpage_image] =>[orig_patent_app_number] => 09480915 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4265884 [patent_doc_number] => 06208552 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-27 [patent_title] => 'Circuit and method for biasing the charging capacitor of a semiconductor memory array' [patent_app_type] => 1 [patent_app_number] => 9/480642 [patent_app_country] => US [patent_app_date] => 2000-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 2583 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/208/06208552.pdf [firstpage_image] =>[orig_patent_app_number] => 480642 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4298564 [patent_doc_number] => 06269033 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-31 [patent_title] => 'Semiconductor memory device having redundancy unit for data line compensation' [patent_app_type] => 1 [patent_app_number] => 9/480619 [patent_app_country] => US [patent_app_date] => 2000-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 9057 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/269/06269033.pdf [firstpage_image] =>[orig_patent_app_number] => 480619 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1437678 [patent_doc_number] => 06356484 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-03-12 [patent_title] => 'Semiconductor memory device' [patent_app_type] => B2 [patent_app_number] => 09/480006 [patent_app_country] => US [patent_app_date] => 2000-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 199 [patent_figures_cnt] => 236 [patent_no_of_words] => 95791 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/356/06356484.pdf [firstpage_image] =>[orig_patent_app_number] => 09480006 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4425571 [patent_doc_number] => 06178125 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-23 [patent_title] => 'Semiconductor memory device preventing repeated use of spare memory cell and repairable by cell substitution up to two times' [patent_app_type] => 1 [patent_app_number] => 9/478335 [patent_app_country] => US [patent_app_date] => 2000-01-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 14 [patent_no_of_words] => 6839 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 306 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/178/06178125.pdf [firstpage_image] =>[orig_patent_app_number] => 478335 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4384464 [patent_doc_number] => 06288956 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-11 [patent_title] => 'Semiconductor device having test function' [patent_app_type] => 1 [patent_app_number] => 9/477717 [patent_app_country] => US [patent_app_date] => 2000-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 3025 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/288/06288956.pdf [firstpage_image] =>[orig_patent_app_number] => 477717 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4317790 [patent_doc_number] => 06327188 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-12-04 [patent_title] => 'Synchronous random access memory' [patent_app_type] => 1 [patent_app_number] => 9/477560 [patent_app_country] => US [patent_app_date] => 2000-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 33 [patent_no_of_words] => 10031 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/327/06327188.pdf [firstpage_image] =>[orig_patent_app_number] => 477560 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4417578 [patent_doc_number] => 06172923 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-09 [patent_title] => 'Programmable read only memory with high speed differential sensing at low operating voltage' [patent_app_type] => 1 [patent_app_number] => 9/478617 [patent_app_country] => US [patent_app_date] => 2000-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 9440 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/172/06172923.pdf [firstpage_image] =>[orig_patent_app_number] => 478617 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4420185 [patent_doc_number] => 06229755 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-08 [patent_title] => 'Wordline driving apparatus in semiconductor memory devices' [patent_app_type] => 1 [patent_app_number] => 9/475019 [patent_app_country] => US [patent_app_date] => 1999-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2908 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/229/06229755.pdf [firstpage_image] =>[orig_patent_app_number] => 475019 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4309682 [patent_doc_number] => 06185132 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-06 [patent_title] => 'Sensing current reduction device for semiconductor memory device and method therefor' [patent_app_type] => 1 [patent_app_number] => 9/475017 [patent_app_country] => US [patent_app_date] => 1999-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3495 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/185/06185132.pdf [firstpage_image] =>[orig_patent_app_number] => 475017 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4185334 [patent_doc_number] => 06141256 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-31 [patent_title] => 'Differential flash memory cell and method for programming same' [patent_app_type] => 1 [patent_app_number] => 9/470079 [patent_app_country] => US [patent_app_date] => 1999-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 4065 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/141/06141256.pdf [firstpage_image] =>[orig_patent_app_number] => 470079 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1437703 [patent_doc_number] => 06356497 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-03-12 [patent_title] => 'Graphics controller integrated circuit without memory interface' [patent_app_type] => B1 [patent_app_number] => 09/467942 [patent_app_country] => US [patent_app_date] => 1999-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 14 [patent_no_of_words] => 5903 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/356/06356497.pdf [firstpage_image] =>[orig_patent_app_number] => 09467942 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4262520 [patent_doc_number] => 06222753 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-24 [patent_title] => 'SRAM cell arrangement and method for manufacturing same' [patent_app_type] => 1 [patent_app_number] => 9/446419 [patent_app_country] => US [patent_app_date] => 1999-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 18 [patent_no_of_words] => 6396 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 521 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/222/06222753.pdf [firstpage_image] =>[orig_patent_app_number] => 446419 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4317131 [patent_doc_number] => 06188625 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-13 [patent_title] => 'Semiconductor memory' [patent_app_type] => 1 [patent_app_number] => 9/461721 [patent_app_country] => US [patent_app_date] => 1999-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 15 [patent_no_of_words] => 5451 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/188/06188625.pdf [firstpage_image] =>[orig_patent_app_number] => 461721 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4262914 [patent_doc_number] => 06222779 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-24 [patent_title] => 'Semiconductor storage device with automatic write/erase function' [patent_app_type] => 1 [patent_app_number] => 9/460644 [patent_app_country] => US [patent_app_date] => 1999-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 34 [patent_figures_cnt] => 50 [patent_no_of_words] => 19347 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/222/06222779.pdf [firstpage_image] =>[orig_patent_app_number] => 460644 [rel_patent_id] =>[rel_patent_doc_number] =>)