Search

Terri L. Filosi

Examiner (ID: 5593, Phone: (571)270-1988 , Office: P/2143 )

Most Active Art Unit
3644
Art Unit(s)
2143, 3762, 3644, 2178
Total Applications
473
Issued Applications
279
Pending Applications
39
Abandoned Applications
165

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18857056 [patent_doc_number] => 11854647 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-12-26 [patent_title] => Voltage level shifter transition time reduction [patent_app_type] => utility [patent_app_number] => 17/388359 [patent_app_country] => US [patent_app_date] => 2021-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 12071 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17388359 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/388359
Voltage level shifter transition time reduction Jul 28, 2021 Issued
Array ( [id] => 17691833 [patent_doc_number] => 20220199126 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-23 [patent_title] => RECEIVERS FOR PERFORMING REFERENCE VOLTAGE TRAINING AND MEMORY SYSTEMS INCLUDING THE SAME [patent_app_type] => utility [patent_app_number] => 17/377654 [patent_app_country] => US [patent_app_date] => 2021-07-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15354 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 279 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17377654 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/377654
Receivers for performing reference voltage training and memory systems including the same Jul 15, 2021 Issued
Array ( [id] => 18415832 [patent_doc_number] => 11670377 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-06-06 [patent_title] => Page buffer and memory device including the same [patent_app_type] => utility [patent_app_number] => 17/375206 [patent_app_country] => US [patent_app_date] => 2021-07-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 33 [patent_no_of_words] => 10117 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17375206 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/375206
Page buffer and memory device including the same Jul 13, 2021 Issued
Array ( [id] => 17318503 [patent_doc_number] => 20210407553 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-12-30 [patent_title] => METHOD AND APPARATUS FOR IMPROVED MEMORY MODULE SUPPLY CURRENT SURGE RESPONSE [patent_app_type] => utility [patent_app_number] => 17/369851 [patent_app_country] => US [patent_app_date] => 2021-07-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6908 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17369851 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/369851
Method and apparatus for improved memory module supply current surge response Jul 6, 2021 Issued
Array ( [id] => 17339194 [patent_doc_number] => 20220005525 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-01-06 [patent_title] => Two-Bit Memory Cell and Circuit Structure Calculated in Memory Thereof [patent_app_type] => utility [patent_app_number] => 17/365841 [patent_app_country] => US [patent_app_date] => 2021-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5958 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 498 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17365841 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/365841
Two-bit memory cell and circuit structure calculated in memory thereof Jun 30, 2021 Issued
Array ( [id] => 18578713 [patent_doc_number] => 11735252 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-08-22 [patent_title] => Multi-level cell programming using optimized multiphase mapping with balanced gray code [patent_app_type] => utility [patent_app_number] => 17/359344 [patent_app_country] => US [patent_app_date] => 2021-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 9347 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 219 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17359344 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/359344
Multi-level cell programming using optimized multiphase mapping with balanced gray code Jun 24, 2021 Issued
Array ( [id] => 17508786 [patent_doc_number] => 20220101889 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-31 [patent_title] => METHOD OF RESETTING STORAGE DEVICE, STORAGE DEVICE PERFORMING THE SAME AND DATA CENTER INCLUDING THE SAME [patent_app_type] => utility [patent_app_number] => 17/346212 [patent_app_country] => US [patent_app_date] => 2021-06-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13979 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17346212 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/346212
Method of resetting storage device, storage device performing the same and data center including the same Jun 11, 2021 Issued
Array ( [id] => 18480996 [patent_doc_number] => 11694747 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-07-04 [patent_title] => Self-selecting memory cells configured to store more than one bit per memory cell [patent_app_type] => utility [patent_app_number] => 17/337806 [patent_app_country] => US [patent_app_date] => 2021-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 16 [patent_no_of_words] => 13112 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17337806 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/337806
Self-selecting memory cells configured to store more than one bit per memory cell Jun 2, 2021 Issued
Array ( [id] => 18408654 [patent_doc_number] => 20230170007 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-01 [patent_title] => INCREASED EFFICIENCY OF CURRENT INDUCED MOTION OF CHIRAL DOMAIN WALLS BY INTERFACE ENGINEERING [patent_app_type] => utility [patent_app_number] => 17/927626 [patent_app_country] => US [patent_app_date] => 2021-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5859 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -23 [patent_words_short_claim] => 44 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17927626 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/927626
INCREASED EFFICIENCY OF CURRENT INDUCED MOTION OF CHIRAL DOMAIN WALLS BY INTERFACE ENGINEERING May 24, 2021 Pending
Array ( [id] => 19046473 [patent_doc_number] => 11935592 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-03-19 [patent_title] => Resistive memory device for writing data and operating method thereof [patent_app_type] => utility [patent_app_number] => 17/328248 [patent_app_country] => US [patent_app_date] => 2021-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 9977 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17328248 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/328248
Resistive memory device for writing data and operating method thereof May 23, 2021 Issued
Array ( [id] => 17217500 [patent_doc_number] => 20210350838 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-11-11 [patent_title] => MEMORY MODULE AND SYSTEM SUPPORTING PARALLEL AND SERIAL ACCESS MODES [patent_app_type] => utility [patent_app_number] => 17/328211 [patent_app_country] => US [patent_app_date] => 2021-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5345 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17328211 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/328211
Memory module and system supporting parallel and serial access modes May 23, 2021 Issued
Array ( [id] => 18415819 [patent_doc_number] => 11670364 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-06-06 [patent_title] => Artificial reality system with reduced SRAM power leakage [patent_app_type] => utility [patent_app_number] => 17/303084 [patent_app_country] => US [patent_app_date] => 2021-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 18 [patent_no_of_words] => 17087 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17303084 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/303084
Artificial reality system with reduced SRAM power leakage May 18, 2021 Issued
Array ( [id] => 18205213 [patent_doc_number] => 11587615 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-02-21 [patent_title] => Cross-point memory compensation [patent_app_type] => utility [patent_app_number] => 17/316271 [patent_app_country] => US [patent_app_date] => 2021-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 9084 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 283 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17316271 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/316271
Cross-point memory compensation May 9, 2021 Issued
Array ( [id] => 18857023 [patent_doc_number] => 11854614 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-12-26 [patent_title] => Electronic device and manufacturing method of electronic device [patent_app_type] => utility [patent_app_number] => 17/315194 [patent_app_country] => US [patent_app_date] => 2021-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 29 [patent_no_of_words] => 11274 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17315194 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/315194
Electronic device and manufacturing method of electronic device May 6, 2021 Issued
Array ( [id] => 18462995 [patent_doc_number] => 11687283 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-06-27 [patent_title] => Memory module interfaces [patent_app_type] => utility [patent_app_number] => 17/306566 [patent_app_country] => US [patent_app_date] => 2021-05-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 6424 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17306566 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/306566
Memory module interfaces May 2, 2021 Issued
Array ( [id] => 19079286 [patent_doc_number] => 11948661 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-04-02 [patent_title] => Methods for tuning command/address bus timing and memory devices and memory systems using the same [patent_app_type] => utility [patent_app_number] => 17/244942 [patent_app_country] => US [patent_app_date] => 2021-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 6423 [patent_no_of_claims] => 45 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17244942 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/244942
Methods for tuning command/address bus timing and memory devices and memory systems using the same Apr 28, 2021 Issued
Array ( [id] => 18292158 [patent_doc_number] => 11621031 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-04-04 [patent_title] => Apparatuses and systems for providing power to a memory [patent_app_type] => utility [patent_app_number] => 17/302206 [patent_app_country] => US [patent_app_date] => 2021-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5740 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17302206 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/302206
Apparatuses and systems for providing power to a memory Apr 26, 2021 Issued
Array ( [id] => 17158769 [patent_doc_number] => 20210319820 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-10-14 [patent_title] => SENSE AMPLIFIER WITH SPLIT CAPACITORS [patent_app_type] => utility [patent_app_number] => 17/241889 [patent_app_country] => US [patent_app_date] => 2021-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19411 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17241889 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/241889
Sense amplifier with split capacitors Apr 26, 2021 Issued
Array ( [id] => 17025200 [patent_doc_number] => 20210249072 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-08-12 [patent_title] => METHOD OF PROGRAMMING MEMORY DEVICE AND RELATED MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 17/241010 [patent_app_country] => US [patent_app_date] => 2021-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3690 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17241010 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/241010
Method of programming memory device and related memory device Apr 25, 2021 Issued
Array ( [id] => 19951074 [patent_doc_number] => 12322444 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-06-03 [patent_title] => Memory devices with controlled wordline ramp rates, and associated systems and methods [patent_app_type] => utility [patent_app_number] => 17/238482 [patent_app_country] => US [patent_app_date] => 2021-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 0 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17238482 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/238482
Memory devices with controlled wordline ramp rates, and associated systems and methods Apr 22, 2021 Issued
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