Search

Terri L. Filosi

Examiner (ID: 5593, Phone: (571)270-1988 , Office: P/2143 )

Most Active Art Unit
3644
Art Unit(s)
2143, 3762, 3644, 2178
Total Applications
473
Issued Applications
279
Pending Applications
39
Abandoned Applications
165

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18950800 [patent_doc_number] => 11894103 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-02-06 [patent_title] => Decoding architecture for word line tiles [patent_app_type] => utility [patent_app_number] => 17/231661 [patent_app_country] => US [patent_app_date] => 2021-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 13 [patent_no_of_words] => 23090 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 359 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17231661 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/231661
Decoding architecture for word line tiles Apr 14, 2021 Issued
Array ( [id] => 18137086 [patent_doc_number] => 11562774 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-01-24 [patent_title] => Semiconductor device having a memory and method of controlling the same between operation modes [patent_app_type] => utility [patent_app_number] => 17/231572 [patent_app_country] => US [patent_app_date] => 2021-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7101 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17231572 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/231572
Semiconductor device having a memory and method of controlling the same between operation modes Apr 14, 2021 Issued
Array ( [id] => 16981176 [patent_doc_number] => 20210225413 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-07-22 [patent_title] => BANK AND CHANNEL STRUCTURE OF STACKED SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 17/222353 [patent_app_country] => US [patent_app_date] => 2021-04-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6597 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17222353 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/222353
Bank and channel structure of stacked semiconductor device Apr 4, 2021 Issued
Array ( [id] => 17971114 [patent_doc_number] => 11488661 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-11-01 [patent_title] => Memory device including memory cells and edge cells [patent_app_type] => utility [patent_app_number] => 17/220701 [patent_app_country] => US [patent_app_date] => 2021-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 6034 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17220701 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/220701
Memory device including memory cells and edge cells Mar 31, 2021 Issued
Array ( [id] => 17900967 [patent_doc_number] => 20220310629 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-29 [patent_title] => EIGHT-TRANSISTOR STATIC RANDOM ACCESS MEMORY CELL [patent_app_type] => utility [patent_app_number] => 17/211903 [patent_app_country] => US [patent_app_date] => 2021-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12459 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17211903 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/211903
Eight-transistor static random access memory cell Mar 24, 2021 Issued
Array ( [id] => 17485684 [patent_doc_number] => 20220093188 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-24 [patent_title] => SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 17/202661 [patent_app_country] => US [patent_app_date] => 2021-03-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 46066 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17202661 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/202661
Semiconductor device Mar 15, 2021 Issued
Array ( [id] => 16981611 [patent_doc_number] => 20210225848 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-07-22 [patent_title] => SEMICONDUCTOR DEVICE WITH FIRST-IN-FIRST-OUT CIRCUIT [patent_app_type] => utility [patent_app_number] => 17/202144 [patent_app_country] => US [patent_app_date] => 2021-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8726 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17202144 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/202144
Semiconductor device with first-in-first-out circuit Mar 14, 2021 Issued
Array ( [id] => 18016121 [patent_doc_number] => 11508424 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-11-22 [patent_title] => Variable resistance memory device [patent_app_type] => utility [patent_app_number] => 17/198495 [patent_app_country] => US [patent_app_date] => 2021-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 16826 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 186 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17198495 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/198495
Variable resistance memory device Mar 10, 2021 Issued
Array ( [id] => 18857034 [patent_doc_number] => 11854625 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-12-26 [patent_title] => Device and method for operating the same [patent_app_type] => utility [patent_app_number] => 17/191892 [patent_app_country] => US [patent_app_date] => 2021-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5035 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17191892 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/191892
Device and method for operating the same Mar 3, 2021 Issued
Array ( [id] => 18174964 [patent_doc_number] => 11574681 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-02-07 [patent_title] => Semiconductor storage device having voltage erasing operation capability and control method thereof [patent_app_type] => utility [patent_app_number] => 17/190856 [patent_app_country] => US [patent_app_date] => 2021-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 6188 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 190 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17190856 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/190856
Semiconductor storage device having voltage erasing operation capability and control method thereof Mar 2, 2021 Issued
Array ( [id] => 17818333 [patent_doc_number] => 11423954 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-08-23 [patent_title] => Semiconductor memory device capable of supporting asynchronous power-down mode, and operating method thereof [patent_app_type] => utility [patent_app_number] => 17/189501 [patent_app_country] => US [patent_app_date] => 2021-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 4377 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17189501 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/189501
Semiconductor memory device capable of supporting asynchronous power-down mode, and operating method thereof Mar 1, 2021 Issued
Array ( [id] => 19198103 [patent_doc_number] => 11995341 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-05-28 [patent_title] => Read/write switching circuit and memory [patent_app_type] => utility [patent_app_number] => 17/595721 [patent_app_country] => US [patent_app_date] => 2021-03-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 9278 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 382 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17595721 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/595721
Read/write switching circuit and memory Feb 28, 2021 Issued
Array ( [id] => 18105298 [patent_doc_number] => 11545192 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-01-03 [patent_title] => System and method of power management in memory design [patent_app_type] => utility [patent_app_number] => 17/185030 [patent_app_country] => US [patent_app_date] => 2021-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 15 [patent_no_of_words] => 13788 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17185030 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/185030
System and method of power management in memory design Feb 24, 2021 Issued
Array ( [id] => 17716411 [patent_doc_number] => 11380409 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-07-05 [patent_title] => Duty adjustment circuit, semiconductor storage device, and memory system [patent_app_type] => utility [patent_app_number] => 17/184849 [patent_app_country] => US [patent_app_date] => 2021-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 32 [patent_no_of_words] => 21127 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17184849 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/184849
Duty adjustment circuit, semiconductor storage device, and memory system Feb 24, 2021 Issued
Array ( [id] => 17833376 [patent_doc_number] => 20220270680 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-08-25 [patent_title] => TECHNOLOGIES FOR CONTROLLING CURRENT THROUGH MEMORY CELLS [patent_app_type] => utility [patent_app_number] => 17/184462 [patent_app_country] => US [patent_app_date] => 2021-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16825 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17184462 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/184462
Technologies for controlling current through memory cells Feb 23, 2021 Issued
Array ( [id] => 17099955 [patent_doc_number] => 20210287746 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-09-16 [patent_title] => MEMORY CELL ARRAY OF MULTI-TIME PROGRAMMABLE NON-VOLATILE MEMORY [patent_app_type] => utility [patent_app_number] => 17/183528 [patent_app_country] => US [patent_app_date] => 2021-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11544 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17183528 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/183528
Memory cell array of multi-time programmable non-volatile memory Feb 23, 2021 Issued
Array ( [id] => 17716400 [patent_doc_number] => 11380398 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-07-05 [patent_title] => Storage device and the read operating method thereof [patent_app_type] => utility [patent_app_number] => 17/182556 [patent_app_country] => US [patent_app_date] => 2021-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 11925 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17182556 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/182556
Storage device and the read operating method thereof Feb 22, 2021 Issued
Array ( [id] => 18431429 [patent_doc_number] => 11676656 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-06-13 [patent_title] => Memory architecture with DC biasing [patent_app_type] => utility [patent_app_number] => 17/168428 [patent_app_country] => US [patent_app_date] => 2021-02-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5984 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17168428 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/168428
Memory architecture with DC biasing Feb 4, 2021 Issued
Array ( [id] => 17893053 [patent_doc_number] => 11456032 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-09-27 [patent_title] => Systems and methods for memory cell accesses [patent_app_type] => utility [patent_app_number] => 17/162031 [patent_app_country] => US [patent_app_date] => 2021-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 10243 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17162031 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/162031
Systems and methods for memory cell accesses Jan 28, 2021 Issued
Array ( [id] => 16995162 [patent_doc_number] => 20210233582 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-07-29 [patent_title] => BIT-LINE VOLTAGE GENERATION CIRCUIT FOR A NON-VOLATILE MEMORY DEVICE AND CORRESPONDING METHOD [patent_app_type] => utility [patent_app_number] => 17/159381 [patent_app_country] => US [patent_app_date] => 2021-01-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6196 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17159381 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/159381
Bit-line voltage generation circuit for a non-volatile memory device and corresponding method Jan 26, 2021 Issued
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