Search

Terri L. Filosi

Examiner (ID: 5593, Phone: (571)270-1988 , Office: P/2143 )

Most Active Art Unit
3644
Art Unit(s)
2143, 3762, 3644, 2178
Total Applications
473
Issued Applications
279
Pending Applications
39
Abandoned Applications
165

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17477058 [patent_doc_number] => 20220084562 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-17 [patent_title] => SEMICONDUCTOR DEVICE FOR STABLE CONTROL OF POWER-DOWN MODE [patent_app_type] => utility [patent_app_number] => 17/150745 [patent_app_country] => US [patent_app_date] => 2021-01-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17186 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17150745 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/150745
Semiconductor device for stable control of power-down mode Jan 14, 2021 Issued
Array ( [id] => 17373380 [patent_doc_number] => 20220028432 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-01-27 [patent_title] => SEMICONDUCTOR APPARATUS AND SEMICONDUCTOR MEMORY APPARATUS [patent_app_type] => utility [patent_app_number] => 17/148201 [patent_app_country] => US [patent_app_date] => 2021-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6368 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17148201 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/148201
Semiconductor apparatus and semiconductor memory apparatus Jan 12, 2021 Issued
Array ( [id] => 18181030 [patent_doc_number] => 20230041759 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-02-09 [patent_title] => FERROELECTRIC MEMORY CIRCUIT AND READING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/791795 [patent_app_country] => US [patent_app_date] => 2021-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14724 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17791795 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/791795
Ferroelectric memory circuit and reading method thereof Jan 7, 2021 Issued
Array ( [id] => 17925675 [patent_doc_number] => 11468934 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-10-11 [patent_title] => Access line disturbance mitigation [patent_app_type] => utility [patent_app_number] => 17/143728 [patent_app_country] => US [patent_app_date] => 2021-01-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 14 [patent_no_of_words] => 21373 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17143728 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/143728
Access line disturbance mitigation Jan 6, 2021 Issued
Array ( [id] => 17574228 [patent_doc_number] => 11322503 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-05-03 [patent_title] => Integrated circuit including at least one memory cell with an antifuse device [patent_app_type] => utility [patent_app_number] => 17/141498 [patent_app_country] => US [patent_app_date] => 2021-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 4288 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17141498 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/141498
Integrated circuit including at least one memory cell with an antifuse device Jan 4, 2021 Issued
Array ( [id] => 16918546 [patent_doc_number] => 20210191638 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-06-24 [patent_title] => VOLTAGE THRESHOLDS IN FLASH DEVICES [patent_app_type] => utility [patent_app_number] => 17/135747 [patent_app_country] => US [patent_app_date] => 2020-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 38586 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17135747 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/135747
VOLTAGE THRESHOLDS IN FLASH DEVICES Dec 27, 2020 Pending
Array ( [id] => 17516628 [patent_doc_number] => 11295787 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-04-05 [patent_title] => Reducing SRAM leakage using scalable switched capacitor regulators [patent_app_type] => utility [patent_app_number] => 17/134765 [patent_app_country] => US [patent_app_date] => 2020-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 11292 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 224 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17134765 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/134765
Reducing SRAM leakage using scalable switched capacitor regulators Dec 27, 2020 Issued
Array ( [id] => 18212172 [patent_doc_number] => 20230058436 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-02-23 [patent_title] => SENSE AMPLIFIER, MEMORY AND METHOD FOR CONTROLLING SENSE AMPLIFIER [patent_app_type] => utility [patent_app_number] => 17/441780 [patent_app_country] => US [patent_app_date] => 2020-12-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7747 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17441780 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/441780
Sense amplifier, memory and method for controlling sense amplifier Dec 24, 2020 Issued
Array ( [id] => 16765293 [patent_doc_number] => 20210110875 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-15 [patent_title] => MEMORY SYSTEM [patent_app_type] => utility [patent_app_number] => 17/131400 [patent_app_country] => US [patent_app_date] => 2020-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 26807 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17131400 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/131400
Memory system Dec 21, 2020 Issued
Array ( [id] => 17924493 [patent_doc_number] => 11467741 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-10-11 [patent_title] => Dynamic peak power management for multi-die operations [patent_app_type] => utility [patent_app_number] => 17/127405 [patent_app_country] => US [patent_app_date] => 2020-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 8393 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17127405 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/127405
Dynamic peak power management for multi-die operations Dec 17, 2020 Issued
Array ( [id] => 17010663 [patent_doc_number] => 20210241824 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-08-05 [patent_title] => SHARED POWER FOOTER CIRCUIT [patent_app_type] => utility [patent_app_number] => 17/119357 [patent_app_country] => US [patent_app_date] => 2020-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5252 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17119357 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/119357
Shared power footer circuit Dec 10, 2020 Issued
Array ( [id] => 16780768 [patent_doc_number] => 20210117847 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-22 [patent_title] => CONSTRUCTING AND PROGRAMMING QUANTUM HARDWARE FOR ROBUST QUANTUM ANNEALING PROCESSES [patent_app_type] => utility [patent_app_number] => 17/115493 [patent_app_country] => US [patent_app_date] => 2020-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6636 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 184 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17115493 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/115493
Constructing and programming quantum hardware for robust quantum annealing processes Dec 7, 2020 Issued
Array ( [id] => 17757978 [patent_doc_number] => 11398276 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-07-26 [patent_title] => Decoder architecture for memory device [patent_app_type] => utility [patent_app_number] => 17/108763 [patent_app_country] => US [patent_app_date] => 2020-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 15830 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17108763 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/108763
Decoder architecture for memory device Nov 30, 2020 Issued
Array ( [id] => 17158759 [patent_doc_number] => 20210319810 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-10-14 [patent_title] => METHOD AND APPARATUS FOR ACCESSING TO DATA IN RESPONSE TO POWER-SUPPLY EVENT [patent_app_type] => utility [patent_app_number] => 17/108681 [patent_app_country] => US [patent_app_date] => 2020-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5798 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17108681 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/108681
Method and apparatus for accessing to data in response to power-supply event Nov 30, 2020 Issued
Array ( [id] => 16765290 [patent_doc_number] => 20210110872 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-04-15 [patent_title] => Semiconductor Memory Having Both Volatile and Non-Volatile Functionality Including Resistance Change Material and Method of Operating [patent_app_type] => utility [patent_app_number] => 17/107904 [patent_app_country] => US [patent_app_date] => 2020-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15585 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17107904 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/107904
Semiconductor memory having both volatile and non-volatile functionality including resistance change material and method of operating Nov 29, 2020 Issued
Array ( [id] => 16715349 [patent_doc_number] => 20210082496 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-03-18 [patent_title] => Read Assist Circuitry for Memory Applications [patent_app_type] => utility [patent_app_number] => 17/107559 [patent_app_country] => US [patent_app_date] => 2020-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6216 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 27 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17107559 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/107559
Read assist circuitry for memory applications Nov 29, 2020 Issued
Array ( [id] => 18331646 [patent_doc_number] => 11636896 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-04-25 [patent_title] => Memory cell array circuit and method of forming the same [patent_app_type] => utility [patent_app_number] => 17/103239 [patent_app_country] => US [patent_app_date] => 2020-11-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 20 [patent_no_of_words] => 14945 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17103239 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/103239
Memory cell array circuit and method of forming the same Nov 23, 2020 Issued
Array ( [id] => 18736945 [patent_doc_number] => 11805701 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-10-31 [patent_title] => Memory and forming methods and control methods thereof [patent_app_type] => utility [patent_app_number] => 17/310366 [patent_app_country] => US [patent_app_date] => 2020-11-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 5814 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17310366 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/310366
Memory and forming methods and control methods thereof Nov 10, 2020 Issued
Array ( [id] => 17599081 [patent_doc_number] => 20220148655 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-05-12 [patent_title] => DRIFT AND NOISE CORRECTED MEMRISTIVE DEVICE [patent_app_type] => utility [patent_app_number] => 17/094744 [patent_app_country] => US [patent_app_date] => 2020-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4973 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17094744 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/094744
Drift and noise corrected memristive device Nov 9, 2020 Issued
Array ( [id] => 16936100 [patent_doc_number] => 20210201989 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-07-01 [patent_title] => MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 17/085420 [patent_app_country] => US [patent_app_date] => 2020-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7831 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17085420 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/085420
Memory device having a comparator circuit Oct 29, 2020 Issued
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