Search

Terri L. Filosi

Examiner (ID: 5593, Phone: (571)270-1988 , Office: P/2143 )

Most Active Art Unit
3644
Art Unit(s)
2143, 3762, 3644, 2178
Total Applications
473
Issued Applications
279
Pending Applications
39
Abandoned Applications
165

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 15806939 [patent_doc_number] => 20200126612 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-04-23 [patent_title] => MODE-DEPENDENT HEATING OF A MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 16/579475 [patent_app_country] => US [patent_app_date] => 2019-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 32979 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16579475 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/579475
Mode-dependent heating of a memory device Sep 22, 2019 Issued
Array ( [id] => 16819694 [patent_doc_number] => 11004531 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-05-11 [patent_title] => Test control circuit, semiconductor memory apparatus and semiconductor system using the test control circuit [patent_app_type] => utility [patent_app_number] => 16/576425 [patent_app_country] => US [patent_app_date] => 2019-09-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6591 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16576425 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/576425
Test control circuit, semiconductor memory apparatus and semiconductor system using the test control circuit Sep 18, 2019 Issued
Array ( [id] => 16574810 [patent_doc_number] => 10896735 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-01-19 [patent_title] => Semiconductor memory device [patent_app_type] => utility [patent_app_number] => 16/564223 [patent_app_country] => US [patent_app_date] => 2019-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 45 [patent_figures_cnt] => 45 [patent_no_of_words] => 24183 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16564223 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/564223
Semiconductor memory device Sep 8, 2019 Issued
Array ( [id] => 16677027 [patent_doc_number] => 20210065793 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-03-04 [patent_title] => REDUCING DISTURBANCE IN CROSSBAR ARRAY CIRCUITS [patent_app_type] => utility [patent_app_number] => 16/558119 [patent_app_country] => US [patent_app_date] => 2019-09-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3692 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16558119 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/558119
Reducing disturbance in crossbar array circuits Aug 31, 2019 Issued
Array ( [id] => 17878360 [patent_doc_number] => 11450381 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-09-20 [patent_title] => Multi-deck memory device including buffer circuitry under array [patent_app_type] => utility [patent_app_number] => 16/546720 [patent_app_country] => US [patent_app_date] => 2019-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 14266 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 293 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16546720 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/546720
Multi-deck memory device including buffer circuitry under array Aug 20, 2019 Issued
Array ( [id] => 16645616 [patent_doc_number] => 10923484 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-02-16 [patent_title] => Integrated circuit including at least one memory cell with an antifuse device [patent_app_type] => utility [patent_app_number] => 16/546002 [patent_app_country] => US [patent_app_date] => 2019-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 4271 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16546002 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/546002
Integrated circuit including at least one memory cell with an antifuse device Aug 19, 2019 Issued
Array ( [id] => 15502835 [patent_doc_number] => 20200051606 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-02-13 [patent_title] => SENSE AMPLIFIER WITH SPLIT CAPACITORS [patent_app_type] => utility [patent_app_number] => 16/544534 [patent_app_country] => US [patent_app_date] => 2019-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19382 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16544534 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/544534
Sense amplifier with split capacitors Aug 18, 2019 Issued
Array ( [id] => 17018197 [patent_doc_number] => 11087842 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-08-10 [patent_title] => Multifunctional memory cells [patent_app_type] => utility [patent_app_number] => 16/536829 [patent_app_country] => US [patent_app_date] => 2019-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 14 [patent_no_of_words] => 18503 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16536829 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/536829
Multifunctional memory cells Aug 8, 2019 Issued
Array ( [id] => 18016119 [patent_doc_number] => 11508422 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-11-22 [patent_title] => Methods for memory power management and memory devices and systems employing the same [patent_app_type] => utility [patent_app_number] => 16/530739 [patent_app_country] => US [patent_app_date] => 2019-08-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 5815 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 191 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16530739 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/530739
Methods for memory power management and memory devices and systems employing the same Aug 1, 2019 Issued
Array ( [id] => 16162675 [patent_doc_number] => 20200219570 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-07-09 [patent_title] => ONE-TIME PROGRAMMABLE (OTP) MEMORY DEVICES AND METHODS OF TESTING OTP MEMORY DEVICES [patent_app_type] => utility [patent_app_number] => 16/524316 [patent_app_country] => US [patent_app_date] => 2019-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9733 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16524316 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/524316
One-time programmable (OTP) memory devices and methods of testing OTP memory devices Jul 28, 2019 Issued
Array ( [id] => 16653159 [patent_doc_number] => 10930350 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-02-23 [patent_title] => Memory device for updating micro-code, memory system including the memory device, and method for operating the memory device [patent_app_type] => utility [patent_app_number] => 16/521225 [patent_app_country] => US [patent_app_date] => 2019-07-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 19 [patent_no_of_words] => 11296 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16521225 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/521225
Memory device for updating micro-code, memory system including the memory device, and method for operating the memory device Jul 23, 2019 Issued
Array ( [id] => 16000349 [patent_doc_number] => 20200176045 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-06-04 [patent_title] => MEMORY SYSTEM AND OPERATING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 16/517232 [patent_app_country] => US [patent_app_date] => 2019-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14748 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 195 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16517232 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/517232
Read latency improvement method and memory system thereof Jul 18, 2019 Issued
Array ( [id] => 15093149 [patent_doc_number] => 20190341386 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-11-07 [patent_title] => METHOD OF FORMING SEMICONDUCTOR MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 16/512306 [patent_app_country] => US [patent_app_date] => 2019-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6391 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16512306 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/512306
Method of forming semiconductor memory device Jul 14, 2019 Issued
Array ( [id] => 16819678 [patent_doc_number] => 11004515 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-05-11 [patent_title] => Semiconductor memory device, controller and memory system having the same [patent_app_type] => utility [patent_app_number] => 16/503851 [patent_app_country] => US [patent_app_date] => 2019-07-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 19 [patent_no_of_words] => 13343 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16503851 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/503851
Semiconductor memory device, controller and memory system having the same Jul 4, 2019 Issued
Array ( [id] => 16172010 [patent_doc_number] => 10713584 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-07-14 [patent_title] => Constructing and programming quantum hardware for robust quantum annealing processes [patent_app_type] => utility [patent_app_number] => 16/453477 [patent_app_country] => US [patent_app_date] => 2019-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 6491 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16453477 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/453477
Constructing and programming quantum hardware for robust quantum annealing processes Jun 25, 2019 Issued
Array ( [id] => 14968549 [patent_doc_number] => 20190311753 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-10-10 [patent_title] => APPARATUSES AND METHODS FOR DETERMINING A PHASE RELATIONSHIP BETWEEN AN INPUT CLOCK SIGNAL AND A MULTIPHASE CLOCK SIGNAL [patent_app_type] => utility [patent_app_number] => 16/452436 [patent_app_country] => US [patent_app_date] => 2019-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8856 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16452436 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/452436
Apparatuses and methods for determining a phase relationship between an input clock signal and a multiphase clock signal Jun 24, 2019 Issued
Array ( [id] => 14967611 [patent_doc_number] => 20190311284 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-10-10 [patent_title] => CONSTRUCTING AND PROGRAMMING QUANTUM HARDWARE FOR ROBUST QUANTUM ANNEALING PROCESSES [patent_app_type] => utility [patent_app_number] => 16/450461 [patent_app_country] => US [patent_app_date] => 2019-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6484 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -5 [patent_words_short_claim] => 209 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16450461 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/450461
Constructing and programming quantum hardware for robust quantum annealing processes Jun 23, 2019 Issued
Array ( [id] => 16463876 [patent_doc_number] => 10847233 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-11-24 [patent_title] => Memory devices and apparatus configured to apply positive voltage levels to data lines for memory cells selected for and inhibited from programming [patent_app_type] => utility [patent_app_number] => 16/435996 [patent_app_country] => US [patent_app_date] => 2019-06-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 7086 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 268 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16435996 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/435996
Memory devices and apparatus configured to apply positive voltage levels to data lines for memory cells selected for and inhibited from programming Jun 9, 2019 Issued
Array ( [id] => 16455788 [patent_doc_number] => 20200365214 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-11-19 [patent_title] => APPARATUS AND METHODS FOR CALIBRATING SENSING OF MEMORY CELL DATA STATES [patent_app_type] => utility [patent_app_number] => 16/414897 [patent_app_country] => US [patent_app_date] => 2019-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15219 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 194 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16414897 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/414897
Apparatus and methods for calibrating sensing of memory cell data states May 16, 2019 Issued
Array ( [id] => 14784383 [patent_doc_number] => 20190267089 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-08-29 [patent_title] => Semiconductor Memory Having Both Volatile and Non-Volatile Functionality Including Resistance Change Material and Method of Operating [patent_app_type] => utility [patent_app_number] => 16/407614 [patent_app_country] => US [patent_app_date] => 2019-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15586 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16407614 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/407614
Semiconductor memory having both volatile and non-volatile functionality including resistance change material and method of operating May 8, 2019 Issued
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