Search

Terri L. Filosi

Examiner (ID: 5593, Phone: (571)270-1988 , Office: P/2143 )

Most Active Art Unit
3644
Art Unit(s)
2143, 3762, 3644, 2178
Total Applications
473
Issued Applications
279
Pending Applications
39
Abandoned Applications
165

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19661785 [patent_doc_number] => 20240428850 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-26 [patent_title] => Dynamic Adjustment of Word Line Timing in Static Dynamic Random Access Memory [patent_app_type] => utility [patent_app_number] => 18/772274 [patent_app_country] => US [patent_app_date] => 2024-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4717 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18772274 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/772274
Dynamic Adjustment of Word Line Timing in Static Dynamic Random Access Memory Jul 14, 2024 Pending
Array ( [id] => 19559621 [patent_doc_number] => 20240371413 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-07 [patent_title] => SYSTEM AND METHOD OF POWER MANAGEMENT IN MEMORY DESIGN [patent_app_type] => utility [patent_app_number] => 18/771349 [patent_app_country] => US [patent_app_date] => 2024-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13842 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18771349 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/771349
SYSTEM AND METHOD OF POWER MANAGEMENT IN MEMORY DESIGN Jul 11, 2024 Pending
Array ( [id] => 19696095 [patent_doc_number] => 20250014640 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-09 [patent_title] => DECODER ARCHITECTURE FOR MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/768922 [patent_app_country] => US [patent_app_date] => 2024-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15909 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18768922 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/768922
DECODER ARCHITECTURE FOR MEMORY DEVICE Jul 9, 2024 Pending
Array ( [id] => 19548653 [patent_doc_number] => 20240365689 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-31 [patent_title] => MEMORY DEVICE, MEMORY ARRAY, AND N-BIT MEMORY UNIT [patent_app_type] => utility [patent_app_number] => 18/764340 [patent_app_country] => US [patent_app_date] => 2024-07-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6231 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18764340 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/764340
MEMORY DEVICE, MEMORY ARRAY, AND N-BIT MEMORY UNIT Jul 3, 2024 Pending
Array ( [id] => 20028499 [patent_doc_number] => 20250166721 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-22 [patent_title] => NONVOLATILE MEMORY DEVICE, STORAGE DEVICE HAVING THE SAME, AND TESTING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/761985 [patent_app_country] => US [patent_app_date] => 2024-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7250 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18761985 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/761985
NONVOLATILE MEMORY DEVICE, STORAGE DEVICE HAVING THE SAME, AND TESTING METHOD THEREOF Jul 1, 2024 Pending
Array ( [id] => 20747189 [patent_doc_number] => 12647119 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-06-02 [patent_title] => Delay locked loop and semiconductor memory device [patent_app_type] => utility [patent_app_number] => 18/756555 [patent_app_country] => US [patent_app_date] => 2024-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 0 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 258 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18756555 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/756555
Delay locked loop and semiconductor memory device Jun 26, 2024 Issued
Array ( [id] => 20429361 [patent_doc_number] => 20250391454 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-12-25 [patent_title] => BIPOLAR DECODERS FOR NONVOLATILE MEMORY [patent_app_type] => utility [patent_app_number] => 18/752697 [patent_app_country] => US [patent_app_date] => 2024-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11524 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 190 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18752697 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/752697
BIPOLAR DECODERS FOR NONVOLATILE MEMORY Jun 23, 2024 Pending
Array ( [id] => 19820702 [patent_doc_number] => 20250078909 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-06 [patent_title] => APPARATUS FOR SMALL SWING DATA TRANSFER [patent_app_type] => utility [patent_app_number] => 18/747986 [patent_app_country] => US [patent_app_date] => 2024-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9495 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 205 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18747986 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/747986
APPARATUS FOR SMALL SWING DATA TRANSFER Jun 18, 2024 Pending
Array ( [id] => 19726917 [patent_doc_number] => 20250029668 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-23 [patent_title] => DISTRIBUTED POWER SUPPLY SWITCHING CIRCUIT FOR EFUSE MEMORY [patent_app_type] => utility [patent_app_number] => 18/744504 [patent_app_country] => US [patent_app_date] => 2024-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3161 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18744504 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/744504
Distributed power supply switching circuit for efuse memory Jun 13, 2024 Issued
Array ( [id] => 20283355 [patent_doc_number] => 20250308597 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-10-02 [patent_title] => PROGRAMMING VOLTAGE SUPPLY AND PROGRAMMING VOLTAGE GENERATING METHOD [patent_app_type] => utility [patent_app_number] => 18/741805 [patent_app_country] => US [patent_app_date] => 2024-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18741805 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/741805
Programming voltage supply and programming voltage generating method Jun 12, 2024 Issued
Array ( [id] => 20422864 [patent_doc_number] => 20250384949 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-12-18 [patent_title] => EQUALIZER WITH TUNABLE CONFIGURATION ACCORDING TO ECC OUTPUT [patent_app_type] => utility [patent_app_number] => 18/741263 [patent_app_country] => US [patent_app_date] => 2024-06-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11877 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18741263 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/741263
EQUALIZER WITH TUNABLE CONFIGURATION ACCORDING TO ECC OUTPUT Jun 11, 2024 Pending
Array ( [id] => 19604429 [patent_doc_number] => 20240395309 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-28 [patent_title] => Methods and Circuits for Power Management of a Memory Module [patent_app_type] => utility [patent_app_number] => 18/734655 [patent_app_country] => US [patent_app_date] => 2024-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2549 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18734655 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/734655
Methods and Circuits for Power Management of a Memory Module Jun 4, 2024 Pending
Array ( [id] => 19452402 [patent_doc_number] => 20240312532 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-19 [patent_title] => SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 18/672202 [patent_app_country] => US [patent_app_date] => 2024-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 46105 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18672202 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/672202
SEMICONDUCTOR DEVICE May 22, 2024 Pending
Array ( [id] => 19850384 [patent_doc_number] => 20250095735 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-20 [patent_title] => INTEGRATED CIRCUIT INCLUDING TERNARY CONTENT ADDRESSABLE MEMORY CELL [patent_app_type] => utility [patent_app_number] => 18/664549 [patent_app_country] => US [patent_app_date] => 2024-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12636 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18664549 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/664549
INTEGRATED CIRCUIT INCLUDING TERNARY CONTENT ADDRESSABLE MEMORY CELL May 14, 2024 Pending
Array ( [id] => 19392476 [patent_doc_number] => 20240282346 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-22 [patent_title] => SEMICONDUCTOR MEMORY DEVICE AND MEMORY SYSTEM HAVING THE SAME [patent_app_type] => utility [patent_app_number] => 18/654527 [patent_app_country] => US [patent_app_date] => 2024-05-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8239 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18654527 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/654527
SEMICONDUCTOR MEMORY DEVICE AND MEMORY SYSTEM HAVING THE SAME May 2, 2024 Pending
Array ( [id] => 19420757 [patent_doc_number] => 20240296881 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-05 [patent_title] => Semiconductor Device and Method for Driving Semiconductor Device [patent_app_type] => utility [patent_app_number] => 18/646415 [patent_app_country] => US [patent_app_date] => 2024-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 36767 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 331 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18646415 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/646415
Semiconductor Device and Method for Driving Semiconductor Device Apr 24, 2024 Pending
Array ( [id] => 19347211 [patent_doc_number] => 20240256174 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-01 [patent_title] => READ/WRITE SWITCHING CIRCUIT AND MEMORY [patent_app_type] => utility [patent_app_number] => 18/631228 [patent_app_country] => US [patent_app_date] => 2024-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9285 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 260 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18631228 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/631228
READ/WRITE SWITCHING CIRCUIT AND MEMORY Apr 9, 2024 Pending
Array ( [id] => 20636585 [patent_doc_number] => 12597466 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-04-07 [patent_title] => Semiconductor memory devices with differential threshold voltages [patent_app_type] => utility [patent_app_number] => 18/628284 [patent_app_country] => US [patent_app_date] => 2024-04-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 1239 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18628284 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/628284
Semiconductor memory devices with differential threshold voltages Apr 4, 2024 Issued
Array ( [id] => 20455751 [patent_doc_number] => 12518811 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-01-06 [patent_title] => Methods for tuning command/address bus timing and memory devices and memory systems using the same [patent_app_type] => utility [patent_app_number] => 18/623355 [patent_app_country] => US [patent_app_date] => 2024-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 1331 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18623355 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/623355
Methods for tuning command/address bus timing and memory devices and memory systems using the same Mar 31, 2024 Issued
Array ( [id] => 20001018 [patent_doc_number] => 20250139240 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-01 [patent_title] => MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/621106 [patent_app_country] => US [patent_app_date] => 2024-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2145 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18621106 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/621106
MEMORY DEVICE Mar 28, 2024 Pending
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