Search

Terri L. Filosi

Examiner (ID: 5593, Phone: (571)270-1988 , Office: P/2143 )

Most Active Art Unit
3644
Art Unit(s)
2143, 3762, 3644, 2178
Total Applications
473
Issued Applications
279
Pending Applications
39
Abandoned Applications
165

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 15299499 [patent_doc_number] => 20190392885 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-12-26 [patent_title] => 3D Memory Array Clusters and Resulting Memory Architecture [patent_app_type] => utility [patent_app_number] => 16/226554 [patent_app_country] => US [patent_app_date] => 2018-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3863 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 192 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16226554 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/226554
3D memory array clusters and resulting memory architecture Dec 18, 2018 Issued
Array ( [id] => 16080167 [patent_doc_number] => 20200194070 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-06-18 [patent_title] => APPARATUS AND METHODS FOR PROGRAMMING MEMORY CELLS USING MULTI-STEP PROGRAMMING PULSES [patent_app_type] => utility [patent_app_number] => 16/223305 [patent_app_country] => US [patent_app_date] => 2018-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16113 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -29 [patent_words_short_claim] => 361 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16223305 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/223305
Apparatus and methods for programming memory cells using multi-step programming pulses Dec 17, 2018 Issued
Array ( [id] => 16218251 [patent_doc_number] => 10734071 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-08-04 [patent_title] => Multi-level cell programming using optimized multiphase mapping with balanced Gray code [patent_app_type] => utility [patent_app_number] => 16/219825 [patent_app_country] => US [patent_app_date] => 2018-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 9274 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 315 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16219825 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/219825
Multi-level cell programming using optimized multiphase mapping with balanced Gray code Dec 12, 2018 Issued
Array ( [id] => 15400735 [patent_doc_number] => 10541027 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-01-21 [patent_title] => Multifunctional memory cells [patent_app_type] => utility [patent_app_number] => 16/218125 [patent_app_country] => US [patent_app_date] => 2018-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 14 [patent_no_of_words] => 18478 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16218125 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/218125
Multifunctional memory cells Dec 11, 2018 Issued
Array ( [id] => 15425921 [patent_doc_number] => 10545889 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-01-28 [patent_title] => High-speed low VT drift receiver [patent_app_type] => utility [patent_app_number] => 16/215603 [patent_app_country] => US [patent_app_date] => 2018-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 11335 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 215 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16215603 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/215603
High-speed low VT drift receiver Dec 9, 2018 Issued
Array ( [id] => 14163551 [patent_doc_number] => 20190108878 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-04-11 [patent_title] => REFLOW PROTECTION [patent_app_type] => utility [patent_app_number] => 16/209152 [patent_app_country] => US [patent_app_date] => 2018-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13253 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16209152 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/209152
Reflow protection Dec 3, 2018 Issued
Array ( [id] => 14110437 [patent_doc_number] => 20190096894 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-03-28 [patent_title] => Memory Cells and Memory Arrays [patent_app_type] => utility [patent_app_number] => 16/204409 [patent_app_country] => US [patent_app_date] => 2018-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10173 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16204409 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/204409
Memory cells and memory arrays Nov 28, 2018 Issued
Array ( [id] => 15045101 [patent_doc_number] => 20190333555 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-10-31 [patent_title] => SEMICONDUCTOR SYSTEM, SEMICONDUCTOR CHIP, AND SEMICONDUCTOR MEMORY SYSTEM INCLUDING THE SEMICONDUCTOR SYSTEM [patent_app_type] => utility [patent_app_number] => 16/203351 [patent_app_country] => US [patent_app_date] => 2018-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7210 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16203351 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/203351
Semiconductor system, semiconductor chip, and semiconductor memory system including the semiconductor system Nov 27, 2018 Issued
Array ( [id] => 15047003 [patent_doc_number] => 20190334506 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-10-31 [patent_title] => LEVEL SHIFTER AND MEMORY SYSTEM INCLUDING THE SAME [patent_app_type] => utility [patent_app_number] => 16/202521 [patent_app_country] => US [patent_app_date] => 2018-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7114 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16202521 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/202521
Level shifter and memory system including the same Nov 27, 2018 Issued
Array ( [id] => 14382711 [patent_doc_number] => 20190165268 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-05-30 [patent_title] => RESISTIVE MEMORY DEVICE AND OPERATION METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 16/200853 [patent_app_country] => US [patent_app_date] => 2018-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2670 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16200853 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/200853
Operation method of resistive memory device Nov 26, 2018 Issued
Array ( [id] => 14348471 [patent_doc_number] => 20190156208 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-05-23 [patent_title] => NEURAL NETWORKS USING CROSS-POINT ARRAY AND PATTERN READOUT METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 16/197651 [patent_app_country] => US [patent_app_date] => 2018-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3755 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16197651 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/197651
Neural networks using cross-point array and pattern readout method thereof Nov 20, 2018 Issued
Array ( [id] => 15427377 [patent_doc_number] => 10546623 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-01-28 [patent_title] => Resistive memory device having memory cell array and system including the same [patent_app_type] => utility [patent_app_number] => 16/195199 [patent_app_country] => US [patent_app_date] => 2018-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 12 [patent_no_of_words] => 10580 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16195199 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/195199
Resistive memory device having memory cell array and system including the same Nov 18, 2018 Issued
Array ( [id] => 15856795 [patent_doc_number] => 10643690 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-05-05 [patent_title] => Transposable feedback field-effect electronic device and array circuit using the same [patent_app_type] => utility [patent_app_number] => 16/181419 [patent_app_country] => US [patent_app_date] => 2018-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 8690 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 212 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16181419 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/181419
Transposable feedback field-effect electronic device and array circuit using the same Nov 5, 2018 Issued
Array ( [id] => 16739036 [patent_doc_number] => 10964702 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-03-30 [patent_title] => Semiconductor device with first-in-first-out circuit [patent_app_type] => utility [patent_app_number] => 16/163471 [patent_app_country] => US [patent_app_date] => 2018-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 18 [patent_no_of_words] => 8708 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 192 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16163471 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/163471
Semiconductor device with first-in-first-out circuit Oct 16, 2018 Issued
Array ( [id] => 15516559 [patent_doc_number] => 10564864 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-02-18 [patent_title] => Method for estimating data retention time in a solid state drive [patent_app_type] => utility [patent_app_number] => 16/151750 [patent_app_country] => US [patent_app_date] => 2018-10-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 5575 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16151750 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/151750
Method for estimating data retention time in a solid state drive Oct 3, 2018 Issued
Array ( [id] => 16926951 [patent_doc_number] => 11048434 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-06-29 [patent_title] => Compute in memory circuits with time-to-digital computation [patent_app_type] => utility [patent_app_number] => 16/147024 [patent_app_country] => US [patent_app_date] => 2018-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 20 [patent_no_of_words] => 20983 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16147024 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/147024
Compute in memory circuits with time-to-digital computation Sep 27, 2018 Issued
Array ( [id] => 13847429 [patent_doc_number] => 20190027199 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-01-24 [patent_title] => APPARATUSES AND METHODS FOR DETERMINING A PHASE RELATIONSHIP BETWEEN AN INPUT CLOCK SIGNAL AND A MULTIPHASE CLOCK SIGNAL [patent_app_type] => utility [patent_app_number] => 16/143082 [patent_app_country] => US [patent_app_date] => 2018-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8830 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16143082 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/143082
Apparatuses and methods for determining a phase relationship between an input clock signal and a multiphase clock signal Sep 25, 2018 Issued
Array ( [id] => 14800683 [patent_doc_number] => 10403349 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-09-03 [patent_title] => Ferroelectric memory cell apparatuses and methods of operating ferroelectric memory cells [patent_app_type] => utility [patent_app_number] => 16/140281 [patent_app_country] => US [patent_app_date] => 2018-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 17 [patent_no_of_words] => 15746 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16140281 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/140281
Ferroelectric memory cell apparatuses and methods of operating ferroelectric memory cells Sep 23, 2018 Issued
Array ( [id] => 13740101 [patent_doc_number] => 20180374520 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-12-27 [patent_title] => Signal Conversion [patent_app_type] => utility [patent_app_number] => 16/117509 [patent_app_country] => US [patent_app_date] => 2018-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5458 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16117509 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/117509
Signal conversion based on complimentary analog signal pairs Aug 29, 2018 Issued
Array ( [id] => 14784307 [patent_doc_number] => 20190267051 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-08-29 [patent_title] => SEMICONDUCTOR DEVICES AND SEMICONDUCTOR SYSTEMS INCLUDING A SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 16/117633 [patent_app_country] => US [patent_app_date] => 2018-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8654 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -27 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16117633 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/117633
Semiconductor devices and semiconductor systems including a semiconductor device Aug 29, 2018 Issued
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