Search

Terri L. Filosi

Examiner (ID: 5593, Phone: (571)270-1988 , Office: P/2143 )

Most Active Art Unit
3644
Art Unit(s)
2143, 3762, 3644, 2178
Total Applications
473
Issued Applications
279
Pending Applications
39
Abandoned Applications
165

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 15984237 [patent_doc_number] => 10672453 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-06-02 [patent_title] => Voltage system providing pump voltage for memory device and method for operating the same [patent_app_type] => utility [patent_app_number] => 15/911586 [patent_app_country] => US [patent_app_date] => 2018-03-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 4985 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15911586 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/911586
Voltage system providing pump voltage for memory device and method for operating the same Mar 4, 2018 Issued
Array ( [id] => 16698522 [patent_doc_number] => 10949119 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-03-16 [patent_title] => Data shaping to reduce error rates in solid state memory devices [patent_app_type] => utility [patent_app_number] => 15/900531 [patent_app_country] => US [patent_app_date] => 2018-02-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 7789 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 212 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15900531 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/900531
Data shaping to reduce error rates in solid state memory devices Feb 19, 2018 Issued
Array ( [id] => 14719575 [patent_doc_number] => 20190250851 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-08-15 [patent_title] => METHOD AND APPARATUS FOR PROGRAMMING FLASH BASED STORAGE USING SEGMENTED WRITES [patent_app_type] => utility [patent_app_number] => 15/897923 [patent_app_country] => US [patent_app_date] => 2018-02-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6394 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -24 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15897923 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/897923
Method and apparatus for programming flash based storage using segmented writes Feb 14, 2018 Issued
Array ( [id] => 15984325 [patent_doc_number] => 10672498 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-06-02 [patent_title] => Repair device and semiconductor device including the same [patent_app_type] => utility [patent_app_number] => 15/887552 [patent_app_country] => US [patent_app_date] => 2018-02-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6862 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15887552 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/887552
Repair device and semiconductor device including the same Feb 1, 2018 Issued
Array ( [id] => 14676041 [patent_doc_number] => 20190237135 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-08-01 [patent_title] => Write Assist Circuitry [patent_app_type] => utility [patent_app_number] => 15/886630 [patent_app_country] => US [patent_app_date] => 2018-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7202 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15886630 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/886630
Write assist circuitry Jan 31, 2018 Issued
Array ( [id] => 14675993 [patent_doc_number] => 20190237111 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-08-01 [patent_title] => Routing Structures for Memory Applications [patent_app_type] => utility [patent_app_number] => 15/881704 [patent_app_country] => US [patent_app_date] => 2018-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8320 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15881704 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/881704
Routing structures for memory applications Jan 25, 2018 Issued
Array ( [id] => 14459851 [patent_doc_number] => 10325899 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-06-18 [patent_title] => Semiconductor device including transistors formed in regions of semiconductor substrate and operation method of the same [patent_app_type] => utility [patent_app_number] => 15/880212 [patent_app_country] => US [patent_app_date] => 2018-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 18018 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 294 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15880212 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/880212
Semiconductor device including transistors formed in regions of semiconductor substrate and operation method of the same Jan 24, 2018 Issued
Array ( [id] => 14628747 [patent_doc_number] => 20190227741 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-07-25 [patent_title] => Register Access in a Distributed Memory Buffer System [patent_app_type] => utility [patent_app_number] => 15/877661 [patent_app_country] => US [patent_app_date] => 2018-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15825 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15877661 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/877661
Register access in a distributed memory buffer system Jan 22, 2018 Issued
Array ( [id] => 15249715 [patent_doc_number] => 10510384 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-12-17 [patent_title] => Intracycle bitline restore in high performance memory [patent_app_type] => utility [patent_app_number] => 15/814969 [patent_app_country] => US [patent_app_date] => 2017-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5578 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15814969 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/814969
Intracycle bitline restore in high performance memory Nov 15, 2017 Issued
Array ( [id] => 14204631 [patent_doc_number] => 10269435 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-04-23 [patent_title] => Reducing program disturb by modifying word line voltages at interface in two-tier stack after program-verify [patent_app_type] => utility [patent_app_number] => 15/814769 [patent_app_country] => US [patent_app_date] => 2017-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 34 [patent_no_of_words] => 18763 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15814769 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/814769
Reducing program disturb by modifying word line voltages at interface in two-tier stack after program-verify Nov 15, 2017 Issued
Array ( [id] => 14642223 [patent_doc_number] => 10365855 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-07-30 [patent_title] => Controller reading data stored in a memory device using buffers, operating method thereof and memory system including controller [patent_app_type] => utility [patent_app_number] => 15/813543 [patent_app_country] => US [patent_app_date] => 2017-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 13 [patent_no_of_words] => 9806 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15813543 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/813543
Controller reading data stored in a memory device using buffers, operating method thereof and memory system including controller Nov 14, 2017 Issued
Array ( [id] => 14644043 [patent_doc_number] => 10366769 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-07-30 [patent_title] => Nonvolatile memory device and programming method for fast and slow cells thereof [patent_app_type] => utility [patent_app_number] => 15/810741 [patent_app_country] => US [patent_app_date] => 2017-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 16 [patent_no_of_words] => 9759 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15810741 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/810741
Nonvolatile memory device and programming method for fast and slow cells thereof Nov 12, 2017 Issued
Array ( [id] => 14558601 [patent_doc_number] => 10347773 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-07-09 [patent_title] => Split gate non-volatile memory (NVM) with improved programming efficiency [patent_app_type] => utility [patent_app_number] => 15/807539 [patent_app_country] => US [patent_app_date] => 2017-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7384 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15807539 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/807539
Split gate non-volatile memory (NVM) with improved programming efficiency Nov 7, 2017 Issued
Array ( [id] => 15789081 [patent_doc_number] => 10628265 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-04-21 [patent_title] => Data backup method for performing post package repair (repair on system) operation [patent_app_type] => utility [patent_app_number] => 15/805622 [patent_app_country] => US [patent_app_date] => 2017-11-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 5859 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15805622 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/805622
Data backup method for performing post package repair (repair on system) operation Nov 6, 2017 Issued
Array ( [id] => 13514621 [patent_doc_number] => 20180308853 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-10-25 [patent_title] => Memory Cells and Memory Arrays [patent_app_type] => utility [patent_app_number] => 15/796611 [patent_app_country] => US [patent_app_date] => 2017-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10174 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 231 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15796611 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/796611
Memory cells and memory arrays Oct 26, 2017 Issued
Array ( [id] => 13468361 [patent_doc_number] => 20180285723 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-10-04 [patent_title] => MEMORY SUBSYSTEM IN CNN BASED DIGITAL IC FOR ARTIFICIAL INTELLIGENCE [patent_app_type] => utility [patent_app_number] => 15/729616 [patent_app_country] => US [patent_app_date] => 2017-10-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3132 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15729616 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/729616
Memory subsystem in CNN based digital IC for artificial intelligence Oct 9, 2017 Issued
Array ( [id] => 15387611 [patent_doc_number] => 10534996 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-01-14 [patent_title] => Memory subsystem in CNN based digital IC for artificial intelligence [patent_app_type] => utility [patent_app_number] => 15/729615 [patent_app_country] => US [patent_app_date] => 2017-10-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 3664 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15729615 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/729615
Memory subsystem in CNN based digital IC for artificial intelligence Oct 9, 2017 Issued
Array ( [id] => 14204573 [patent_doc_number] => 10269404 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-04-23 [patent_title] => Resistance change memory [patent_app_type] => utility [patent_app_number] => 15/727053 [patent_app_country] => US [patent_app_date] => 2017-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 15 [patent_no_of_words] => 7125 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15727053 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/727053
Resistance change memory Oct 5, 2017 Issued
Array ( [id] => 13292933 [patent_doc_number] => 10157665 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-12-18 [patent_title] => Word-line enable pulse generator, SRAM and method for adjusting word-line enable time of SRAM [patent_app_type] => utility [patent_app_number] => 15/725521 [patent_app_country] => US [patent_app_date] => 2017-10-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5802 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15725521 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/725521
Word-line enable pulse generator, SRAM and method for adjusting word-line enable time of SRAM Oct 4, 2017 Issued
Array ( [id] => 13018797 [patent_doc_number] => 10032514 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-07-24 [patent_title] => Semiconductor memory having both volatile and non-volatile functionality including resistance change material and method of operating [patent_app_type] => utility [patent_app_number] => 15/724651 [patent_app_country] => US [patent_app_date] => 2017-10-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 18 [patent_no_of_words] => 15703 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15724651 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/724651
Semiconductor memory having both volatile and non-volatile functionality including resistance change material and method of operating Oct 3, 2017 Issued
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