Search

Terri L. Filosi

Examiner (ID: 5593, Phone: (571)270-1988 , Office: P/2143 )

Most Active Art Unit
3644
Art Unit(s)
2143, 3762, 3644, 2178
Total Applications
473
Issued Applications
279
Pending Applications
39
Abandoned Applications
165

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 16536251 [patent_doc_number] => 10878864 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-12-29 [patent_title] => Multiple data rate memory [patent_app_type] => utility [patent_app_number] => 16/081509 [patent_app_country] => US [patent_app_date] => 2017-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 16 [patent_no_of_words] => 8072 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16081509 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/081509
Multiple data rate memory Feb 26, 2017 Issued
Array ( [id] => 12208964 [patent_doc_number] => 20180054190 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-02-22 [patent_title] => 'DATA LATCH CIRCUIT' [patent_app_type] => utility [patent_app_number] => 15/442685 [patent_app_country] => US [patent_app_date] => 2017-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 10895 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15442685 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/442685
Data latch circuit Feb 25, 2017 Issued
Array ( [id] => 16217052 [patent_doc_number] => 10732863 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-08-04 [patent_title] => Memory system storing block protection information [patent_app_type] => utility [patent_app_number] => 15/439712 [patent_app_country] => US [patent_app_date] => 2017-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 31 [patent_no_of_words] => 10166 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 245 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15439712 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/439712
Memory system storing block protection information Feb 21, 2017 Issued
Array ( [id] => 11854669 [patent_doc_number] => 20170229161 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-08-10 [patent_title] => 'DIGITALLY TRIMMABLE INTEGRATED RESISTORS INCLUDING RESISTIVE MEMORY ELEMENTS' [patent_app_type] => utility [patent_app_number] => 15/439800 [patent_app_country] => US [patent_app_date] => 2017-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 9493 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15439800 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/439800
Digitally trimmable integrated resistors including resistive memory elements Feb 21, 2017 Issued
Array ( [id] => 11666207 [patent_doc_number] => 20170154925 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-06-01 [patent_title] => 'METHOD OF FABRICATING MEMORY ARRAY HAVING DIVIDED APART BIT LINES AND PARTIALLY DIVIDED BIT LINE SELECTOR SWITCHES' [patent_app_type] => utility [patent_app_number] => 15/430888 [patent_app_country] => US [patent_app_date] => 2017-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 31 [patent_no_of_words] => 28033 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15430888 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/430888
Method of fabricating memory array having divided apart bit lines and partially divided bit line selector switches Feb 12, 2017 Issued
Array ( [id] => 12195349 [patent_doc_number] => 09899084 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-02-20 [patent_title] => 'Data storage method and phase change memory' [patent_app_type] => utility [patent_app_number] => 15/412509 [patent_app_country] => US [patent_app_date] => 2017-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 9718 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15412509 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/412509
Data storage method and phase change memory Jan 22, 2017 Issued
Array ( [id] => 11622902 [patent_doc_number] => 20170133090 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-05-11 [patent_title] => 'Data Storage Method and Phase Change Memory' [patent_app_type] => utility [patent_app_number] => 15/412795 [patent_app_country] => US [patent_app_date] => 2017-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 9759 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15412795 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/412795
Data storage method and phase change memory Jan 22, 2017 Issued
Array ( [id] => 12207412 [patent_doc_number] => 20180052638 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-02-22 [patent_title] => 'MEMORY DEVICE, MEMORY SYSTEM HAVING THE SAME, AND OPERATING METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 15/395772 [patent_app_country] => US [patent_app_date] => 2016-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 12984 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15395772 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/395772
Memory device detecting last erased page, memory system having the same, and operating method thereof Dec 29, 2016 Issued
Array ( [id] => 12989323 [patent_doc_number] => 20170345500 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-11-30 [patent_title] => MULTIPLE CYCLE SEARCH CONTENT ADDRESSABLE MEMORY [patent_app_type] => utility [patent_app_number] => 15/369823 [patent_app_country] => US [patent_app_date] => 2016-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10815 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 46 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15369823 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/369823
Multiple cycle search content addressable memory Dec 4, 2016 Issued
Array ( [id] => 12800089 [patent_doc_number] => 20180158532 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-06-07 [patent_title] => PARALLEL PROGRAMMING OF ONE TIME PROGRAMMABLE MEMORY ARRAY FOR REDUCED TEST TIME [patent_app_type] => utility [patent_app_number] => 15/367815 [patent_app_country] => US [patent_app_date] => 2016-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4417 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15367815 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/367815
Parallel programming of one time programmable memory array for reduced test time Dec 1, 2016 Issued
Array ( [id] => 12372102 [patent_doc_number] => 09958917 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-05-01 [patent_title] => Generalized resettable memory [patent_app_type] => utility [patent_app_number] => 15/368457 [patent_app_country] => US [patent_app_date] => 2016-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 10847 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 257 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15368457 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/368457
Generalized resettable memory Dec 1, 2016 Issued
Array ( [id] => 14151163 [patent_doc_number] => 10255965 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-04-09 [patent_title] => Memory circuit capable of being quickly written in data [patent_app_type] => utility [patent_app_number] => 15/356681 [patent_app_country] => US [patent_app_date] => 2016-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4031 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15356681 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/356681
Memory circuit capable of being quickly written in data Nov 20, 2016 Issued
Array ( [id] => 12758887 [patent_doc_number] => 20180144797 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-05-24 [patent_title] => INTEGRATED CIRCUIT SYSTEM WITH NON-VOLATILE MEMORY STRESS SUPPRESSION AND METHOD OF MANUFACTURE THEREOF [patent_app_type] => utility [patent_app_number] => 15/356277 [patent_app_country] => US [patent_app_date] => 2016-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10287 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15356277 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/356277
Integrated circuit system with non-volatile memory stress suppression and method of manufacture thereof Nov 17, 2016 Issued
Array ( [id] => 12758887 [patent_doc_number] => 20180144797 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-05-24 [patent_title] => INTEGRATED CIRCUIT SYSTEM WITH NON-VOLATILE MEMORY STRESS SUPPRESSION AND METHOD OF MANUFACTURE THEREOF [patent_app_type] => utility [patent_app_number] => 15/356277 [patent_app_country] => US [patent_app_date] => 2016-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10287 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15356277 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/356277
Integrated circuit system with non-volatile memory stress suppression and method of manufacture thereof Nov 17, 2016 Issued
Array ( [id] => 11911008 [patent_doc_number] => 09779827 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-10-03 [patent_title] => 'Voltage control circuit for memory cell and the method thereof' [patent_app_type] => utility [patent_app_number] => 15/355021 [patent_app_country] => US [patent_app_date] => 2016-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 5236 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15355021 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/355021
Voltage control circuit for memory cell and the method thereof Nov 16, 2016 Issued
Array ( [id] => 13921111 [patent_doc_number] => 10204679 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-02-12 [patent_title] => Highly compact non-volatile memory and method thereof [patent_app_type] => utility [patent_app_number] => 15/348847 [patent_app_country] => US [patent_app_date] => 2016-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 32 [patent_no_of_words] => 12621 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15348847 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/348847
Highly compact non-volatile memory and method thereof Nov 9, 2016 Issued
Array ( [id] => 12228861 [patent_doc_number] => 09916104 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-03-13 [patent_title] => 'Techniques for entry to a lower power state for a memory device' [patent_app_type] => utility [patent_app_number] => 15/344809 [patent_app_country] => US [patent_app_date] => 2016-11-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 10601 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15344809 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/344809
Techniques for entry to a lower power state for a memory device Nov 6, 2016 Issued
Array ( [id] => 12046256 [patent_doc_number] => 09823858 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-11-21 [patent_title] => 'Nonvolatile memory interface for metadata shadowing' [patent_app_type] => utility [patent_app_number] => 15/343861 [patent_app_country] => US [patent_app_date] => 2016-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 13 [patent_no_of_words] => 4922 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15343861 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/343861
Nonvolatile memory interface for metadata shadowing Nov 3, 2016 Issued
Array ( [id] => 12019505 [patent_doc_number] => 09812214 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-11-07 [patent_title] => 'Nonvolatile memory device, storage device including nonvolatile memory device and operating method of nonvolatile memory device' [patent_app_type] => utility [patent_app_number] => 15/340957 [patent_app_country] => US [patent_app_date] => 2016-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 17024 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 212 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15340957 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/340957
Nonvolatile memory device, storage device including nonvolatile memory device and operating method of nonvolatile memory device Oct 31, 2016 Issued
Array ( [id] => 11918172 [patent_doc_number] => 09786363 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-10-10 [patent_title] => 'Word-line enable pulse generator, SRAM and method for adjusting word-line enable time of SRAM' [patent_app_type] => utility [patent_app_number] => 15/340879 [patent_app_country] => US [patent_app_date] => 2016-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6418 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15340879 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/340879
Word-line enable pulse generator, SRAM and method for adjusting word-line enable time of SRAM Oct 31, 2016 Issued
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