Search

Terri L. Filosi

Examiner (ID: 5593, Phone: (571)270-1988 , Office: P/2143 )

Most Active Art Unit
3644
Art Unit(s)
2143, 3762, 3644, 2178
Total Applications
473
Issued Applications
279
Pending Applications
39
Abandoned Applications
165

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 11532380 [patent_doc_number] => 20170092358 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-03-30 [patent_title] => 'CONTENT ADDRESSABLE MEMORY WITH AN ORDERED SEQUENCE' [patent_app_type] => utility [patent_app_number] => 14/863711 [patent_app_country] => US [patent_app_date] => 2015-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 6740 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14863711 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/863711
Content addressable memory with an ordered sequence Sep 23, 2015 Issued
Array ( [id] => 12040223 [patent_doc_number] => 09818458 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-11-14 [patent_title] => 'Techniques for entry to a lower power state for a memory device' [patent_app_type] => utility [patent_app_number] => 14/862269 [patent_app_country] => US [patent_app_date] => 2015-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 10559 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14862269 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/862269
Techniques for entry to a lower power state for a memory device Sep 22, 2015 Issued
Array ( [id] => 11503216 [patent_doc_number] => 20170077400 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-03-16 [patent_title] => 'ASYMMETRIC CORRELATED ELECTRON SWITCH OPERATION' [patent_app_type] => utility [patent_app_number] => 14/850213 [patent_app_country] => US [patent_app_date] => 2015-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 9651 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14850213 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/850213
Asymmetric correlated electron switch operation Sep 9, 2015 Issued
Array ( [id] => 10492957 [patent_doc_number] => 20150377978 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-12-31 [patent_title] => 'SECONDARY BATTERY STATE DETECTING DEVICE AND SECONDARY BATTERY STATE DETECTING METHOD' [patent_app_type] => utility [patent_app_number] => 14/846682 [patent_app_country] => US [patent_app_date] => 2015-09-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5353 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14846682 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/846682
Secondary battery state detecting device and secondary battery state detecting method Sep 3, 2015 Issued
Array ( [id] => 10495049 [patent_doc_number] => 20150380071 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-12-31 [patent_title] => 'CIRCUIT AND METHOD FOR IMPRINT REDUCTION IN FRAM MEMORIES' [patent_app_type] => utility [patent_app_number] => 14/846350 [patent_app_country] => US [patent_app_date] => 2015-09-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5948 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14846350 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/846350
Circuit and method for imprint reduction in FRAM memories Sep 3, 2015 Issued
Array ( [id] => 11214994 [patent_doc_number] => 09444036 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-09-13 [patent_title] => 'Implementing segregated media based magnetic memory' [patent_app_type] => utility [patent_app_number] => 14/835543 [patent_app_country] => US [patent_app_date] => 2015-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 37 [patent_figures_cnt] => 52 [patent_no_of_words] => 6398 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14835543 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/835543
Implementing segregated media based magnetic memory Aug 24, 2015 Issued
Array ( [id] => 10470272 [patent_doc_number] => 20150355288 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-12-10 [patent_title] => 'SECONDARY BATTERY DEGRADATION DETERMINATION METHOD AND SECONDARY BATTERY DEGRADATION DETERMINATION DEVICE' [patent_app_type] => utility [patent_app_number] => 14/829035 [patent_app_country] => US [patent_app_date] => 2015-08-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7481 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14829035 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/829035
Secondary battery degradation determination method and secondary battery degradation determination device Aug 17, 2015 Issued
Array ( [id] => 10652446 [patent_doc_number] => 09368715 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-06-14 [patent_title] => 'Reducing source loading effect in spin torque transfer magnetoresistive random access memory (STT-MRAM)' [patent_app_type] => utility [patent_app_number] => 14/822295 [patent_app_country] => US [patent_app_date] => 2015-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 9558 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14822295 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/822295
Reducing source loading effect in spin torque transfer magnetoresistive random access memory (STT-MRAM) Aug 9, 2015 Issued
Array ( [id] => 10455070 [patent_doc_number] => 20150340085 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-11-26 [patent_title] => 'TRACKING BIT CELL AND METHOD' [patent_app_type] => utility [patent_app_number] => 14/817269 [patent_app_country] => US [patent_app_date] => 2015-08-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 7532 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14817269 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/817269
Tracking bit cell and method Aug 3, 2015 Issued
Array ( [id] => 12115197 [patent_doc_number] => 09871193 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-01-16 [patent_title] => 'Methods of producing and controlling tunneling electroresistance and tunneling magnetoresistance in a multiferroic tunnel junction' [patent_app_type] => utility [patent_app_number] => 14/818075 [patent_app_country] => US [patent_app_date] => 2015-08-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 27 [patent_no_of_words] => 10909 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14818075 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/818075
Methods of producing and controlling tunneling electroresistance and tunneling magnetoresistance in a multiferroic tunnel junction Aug 3, 2015 Issued
Array ( [id] => 10440264 [patent_doc_number] => 20150325276 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-11-12 [patent_title] => 'BIPOLAR LOGIC GATES ON MOS-BASED MEMORY CHIPS' [patent_app_type] => utility [patent_app_number] => 14/801700 [patent_app_country] => US [patent_app_date] => 2015-07-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 8875 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14801700 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/801700
Bipolar logic gates on MOS-based memory chips Jul 15, 2015 Issued
Array ( [id] => 11328026 [patent_doc_number] => 20160358637 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-12-08 [patent_title] => 'MULTI-BANK MEMORY WITH LINE TRACKING LOOP' [patent_app_type] => utility [patent_app_number] => 14/751820 [patent_app_country] => US [patent_app_date] => 2015-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 12738 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14751820 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/751820
Multi-bank memory with line tracking loop Jun 25, 2015 Issued
Array ( [id] => 11483064 [patent_doc_number] => 09589615 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-03-07 [patent_title] => 'Digitally trimmable integrated resistors including resistive memory elements' [patent_app_type] => utility [patent_app_number] => 14/750670 [patent_app_country] => US [patent_app_date] => 2015-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 17 [patent_no_of_words] => 9429 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14750670 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/750670
Digitally trimmable integrated resistors including resistive memory elements Jun 24, 2015 Issued
Array ( [id] => 11430793 [patent_doc_number] => 09569109 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-02-14 [patent_title] => 'Nonvolatile memory interface for metadata shadowing' [patent_app_type] => utility [patent_app_number] => 14/747976 [patent_app_country] => US [patent_app_date] => 2015-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 13 [patent_no_of_words] => 5083 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14747976 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/747976
Nonvolatile memory interface for metadata shadowing Jun 22, 2015 Issued
Array ( [id] => 11599512 [patent_doc_number] => 09646688 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-05-09 [patent_title] => 'Three dimensional non-volatile storage with connected word lines' [patent_app_type] => utility [patent_app_number] => 14/746003 [patent_app_country] => US [patent_app_date] => 2015-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 56 [patent_figures_cnt] => 64 [patent_no_of_words] => 32154 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 349 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14746003 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/746003
Three dimensional non-volatile storage with connected word lines Jun 21, 2015 Issued
Array ( [id] => 10590384 [patent_doc_number] => 09312004 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-04-12 [patent_title] => 'Driver for semiconductor memory and system including the same' [patent_app_type] => utility [patent_app_number] => 14/746394 [patent_app_country] => US [patent_app_date] => 2015-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 16 [patent_no_of_words] => 6281 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 193 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14746394 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/746394
Driver for semiconductor memory and system including the same Jun 21, 2015 Issued
Array ( [id] => 11353458 [patent_doc_number] => 20160372198 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-12-22 [patent_title] => 'MEMORY DEVICE HAVING ONLY THE TOP POLY CUT' [patent_app_type] => utility [patent_app_number] => 14/742944 [patent_app_country] => US [patent_app_date] => 2015-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 4112 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14742944 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/742944
Memory device having only the top poly cut Jun 17, 2015 Issued
Array ( [id] => 11353462 [patent_doc_number] => 20160372202 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-12-22 [patent_title] => 'NON-VOLATILE MEMORY DEVICE HAVING MULTIPLE STRING SELECT LINES' [patent_app_type] => utility [patent_app_number] => 14/742054 [patent_app_country] => US [patent_app_date] => 2015-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 7111 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14742054 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/742054
Non-volatile memory device having multiple string select lines Jun 16, 2015 Issued
Array ( [id] => 11321418 [patent_doc_number] => 09520163 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-12-13 [patent_title] => 'Regulator circuit and semiconductor memory apparatus having the same' [patent_app_type] => utility [patent_app_number] => 14/740400 [patent_app_country] => US [patent_app_date] => 2015-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 4294 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14740400 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/740400
Regulator circuit and semiconductor memory apparatus having the same Jun 15, 2015 Issued
Array ( [id] => 10425906 [patent_doc_number] => 20150310917 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-10-29 [patent_title] => 'Semiconductor Memory Having Both Volatile and Non-Volatile Functionality Including Resistance Change Material and Method of Operating' [patent_app_type] => utility [patent_app_number] => 14/738349 [patent_app_country] => US [patent_app_date] => 2015-06-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 15983 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14738349 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/738349
Semiconductor memory having both volatile and non-volatile functionality including resistance change material and method of operating Jun 11, 2015 Issued
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