
Terri L. Filosi
Examiner (ID: 5593, Phone: (571)270-1988 , Office: P/2143 )
| Most Active Art Unit | 3644 |
| Art Unit(s) | 2143, 3762, 3644, 2178 |
| Total Applications | 473 |
| Issued Applications | 279 |
| Pending Applications | 39 |
| Abandoned Applications | 165 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 20266798
[patent_doc_number] => 12437794
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-10-07
[patent_title] => Method of controlling row hammer and a memory device
[patent_app_type] => utility
[patent_app_number] => 18/610420
[patent_app_country] => US
[patent_app_date] => 2024-03-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 12
[patent_no_of_words] => 2533
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 209
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18610420
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/610420 | Method of controlling row hammer and a memory device | Mar 19, 2024 | Issued |
Array
(
[id] => 19634340
[patent_doc_number] => 20240412789
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-12-12
[patent_title] => NON -VOLATILE MEMORY DEVICE AND OPERATION METHOD THEREOF
[patent_app_type] => utility
[patent_app_number] => 18/607850
[patent_app_country] => US
[patent_app_date] => 2024-03-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 18909
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 90
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18607850
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/607850 | NON -VOLATILE MEMORY DEVICE AND OPERATION METHOD THEREOF | Mar 17, 2024 | Pending |
Array
(
[id] => 19269043
[patent_doc_number] => 20240212747
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-06-27
[patent_title] => SHARED POWER FOOTER CIRCUIT
[patent_app_type] => utility
[patent_app_number] => 18/601512
[patent_app_country] => US
[patent_app_date] => 2024-03-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5269
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => 0
[patent_words_short_claim] => 136
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18601512
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/601512 | Shared power footer circuit | Mar 10, 2024 | Issued |
Array
(
[id] => 19467665
[patent_doc_number] => 20240321335
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-09-26
[patent_title] => MAGNETIC MEMORY DEVICE
[patent_app_type] => utility
[patent_app_number] => 18/599540
[patent_app_country] => US
[patent_app_date] => 2024-03-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 12933
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 202
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18599540
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/599540 | Magnetic memory device | Mar 7, 2024 | Issued |
Array
(
[id] => 19252464
[patent_doc_number] => 20240203461
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-06-20
[patent_title] => HEADER CIRCUIT PLACEMENT IN MEMORY DEVICE
[patent_app_type] => utility
[patent_app_number] => 18/595035
[patent_app_country] => US
[patent_app_date] => 2024-03-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8857
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18595035
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/595035 | Header circuit placement in memory device | Mar 3, 2024 | Issued |
Array
(
[id] => 20597924
[patent_doc_number] => 12581661
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2026-03-17
[patent_title] => Crossbar array device applicable to graph data analysis, nueromorphic device including the same, operation method of crossbar array device and graph data analysis method using crossbar array device
[patent_app_type] => utility
[patent_app_number] => 18/593370
[patent_app_country] => US
[patent_app_date] => 2024-03-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 34
[patent_figures_cnt] => 44
[patent_no_of_words] => 7925
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 101
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18593370
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/593370 | Crossbar array device applicable to graph data analysis, nueromorphic device including the same, operation method of crossbar array device and graph data analysis method using crossbar array device | Feb 29, 2024 | Issued |
Array
(
[id] => 19435747
[patent_doc_number] => 20240304245
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-09-12
[patent_title] => SEMICONDUCTOR MEMORY DEVICE
[patent_app_type] => utility
[patent_app_number] => 18/593570
[patent_app_country] => US
[patent_app_date] => 2024-03-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 18568
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -9
[patent_words_short_claim] => 197
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18593570
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/593570 | Semiconductor memory device performing multi-bit programming using sequential write operations with reduced latch count | Feb 29, 2024 | Issued |
Array
(
[id] => 20774548
[patent_doc_number] => 12658227
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2026-06-16
[patent_title] => Memory sub-system management based on dynamic control of wordline start voltage
[patent_app_type] => utility
[patent_app_number] => 18/587427
[patent_app_country] => US
[patent_app_date] => 2024-02-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 1173
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 129
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18587427
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/587427 | Memory sub-system management based on dynamic control of wordline start voltage | Feb 25, 2024 | Issued |
Array
(
[id] => 20611013
[patent_doc_number] => 12586617
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2026-03-24
[patent_title] => Memory module and system supporting parallel and serial access modes
[patent_app_type] => utility
[patent_app_number] => 18/584434
[patent_app_country] => US
[patent_app_date] => 2024-02-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 11
[patent_no_of_words] => 0
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 68
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18584434
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/584434 | Memory module and system supporting parallel and serial access modes | Feb 21, 2024 | Issued |
Array
(
[id] => 19865994
[patent_doc_number] => 20250104780
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-03-27
[patent_title] => CURRENT BIAS CIRCUIT, MEMORY DEVICE AND MEMORY SYSTEM
[patent_app_type] => utility
[patent_app_number] => 18/442040
[patent_app_country] => US
[patent_app_date] => 2024-02-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 10993
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 84
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18442040
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/442040 | CURRENT BIAS CIRCUIT, MEMORY DEVICE AND MEMORY SYSTEM | Feb 13, 2024 | Pending |
Array
(
[id] => 19363930
[patent_doc_number] => 20240265964
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-08-08
[patent_title] => FLASH MEMORY AND WEAR LEVELING METHOD THEREOF
[patent_app_type] => utility
[patent_app_number] => 18/429450
[patent_app_country] => US
[patent_app_date] => 2024-02-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7795
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 111
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18429450
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/429450 | Flash memory and wear leveling method thereof | Jan 31, 2024 | Issued |
Array
(
[id] => 20010847
[patent_doc_number] => 20250149069
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-05-08
[patent_title] => SEMICONDUCTOR APPARATUS AND MEMORY SYSTEM INCLUDING THE SAME
[patent_app_type] => utility
[patent_app_number] => 18/428302
[patent_app_country] => US
[patent_app_date] => 2024-01-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 0
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -16
[patent_words_short_claim] => 72
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18428302
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/428302 | Semiconductor apparatus with active internal power control and memory system including the same | Jan 30, 2024 | Issued |
Array
(
[id] => 20416628
[patent_doc_number] => 12499917
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-12-16
[patent_title] => Inrush current management in a memory array
[patent_app_type] => utility
[patent_app_number] => 18/427637
[patent_app_country] => US
[patent_app_date] => 2024-01-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 2461
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 130
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18427637
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/427637 | Inrush current management in a memory array | Jan 29, 2024 | Issued |
Array
(
[id] => 19850398
[patent_doc_number] => 20250095749
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-03-20
[patent_title] => OPERATION METHOD OF MEMORY SYSTEM, DATA READ METHOD OF MEMORY AND MEMORY SYSTEM
[patent_app_type] => utility
[patent_app_number] => 18/424043
[patent_app_country] => US
[patent_app_date] => 2024-01-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 10456
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 131
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18424043
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/424043 | Offset voltage based operation method of memory system, data read method of memory and memory system | Jan 25, 2024 | Issued |
Array
(
[id] => 19160843
[patent_doc_number] => 20240153550
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-05-09
[patent_title] => MEMORY DEVICE INCLUDING MEMORY CELLS AND EDGE CELLS
[patent_app_type] => utility
[patent_app_number] => 18/412380
[patent_app_country] => US
[patent_app_date] => 2024-01-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6079
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 93
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18412380
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/412380 | Memory device including memory cells and edge cells | Jan 11, 2024 | Issued |
Array
(
[id] => 19160851
[patent_doc_number] => 20240153558
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-05-09
[patent_title] => RESISTIVE MEMORY WITH ENHANCED REDUNDANCY WRITING
[patent_app_type] => utility
[patent_app_number] => 18/411758
[patent_app_country] => US
[patent_app_date] => 2024-01-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5642
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 106
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18411758
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/411758 | Resistive memory with enhanced redundancy writing | Jan 11, 2024 | Issued |
Array
(
[id] => 19175827
[patent_doc_number] => 20240161801
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-05-16
[patent_title] => DECODING ARCHITECTURE FOR WORD LINE TILES
[patent_app_type] => utility
[patent_app_number] => 18/409397
[patent_app_country] => US
[patent_app_date] => 2024-01-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 23120
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 95
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18409397
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/409397 | DECODING ARCHITECTURE FOR WORD LINE TILES | Jan 9, 2024 | Pending |
Array
(
[id] => 19515394
[patent_doc_number] => 20240347080
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-10-17
[patent_title] => SEMICONDUCTOR DEVICE
[patent_app_type] => utility
[patent_app_number] => 18/406726
[patent_app_country] => US
[patent_app_date] => 2024-01-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 11434
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 194
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18406726
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/406726 | SEMICONDUCTOR DEVICE | Jan 7, 2024 | Pending |
Array
(
[id] => 20088539
[patent_doc_number] => 20250218475
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-07-03
[patent_title] => Compute-in-Memory with Current Transition Detection
[patent_app_type] => utility
[patent_app_number] => 18/403010
[patent_app_country] => US
[patent_app_date] => 2024-01-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 0
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 41
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18403010
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/403010 | Compute-in-Memory with Current Transition Detection | Jan 2, 2024 | Pending |
Array
(
[id] => 20071875
[patent_doc_number] => 20250210097
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-06-26
[patent_title] => MEMORY DEVICE AND METHOD FOR OPERATING THE SAME
[patent_app_type] => utility
[patent_app_number] => 18/396210
[patent_app_country] => US
[patent_app_date] => 2023-12-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 0
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 109
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18396210
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/396210 | Memory device and method for operating the same | Dec 25, 2023 | Issued |