Terri L. Filosi

Array ( [id] => 10638563 [patent_doc_number] => 09356074 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-05-31 [patent_title] => 'Memory array having divided apart bit lines and partially divided bit line selector switches' [patent_app_type] => utility [patent_app_number] => 14/543690 [patent_app_country] => US [patent_app_date] => 2014-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 33 [patent_no_of_words] => 28033 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 309 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14543690 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11094597 [patent_doc_number] => 20160291565 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-10-06 [patent_title] => 'AUTOMATION SYSTEM' [patent_app_type] => utility [patent_app_number] => 15/037244 [patent_app_country] => US [patent_app_date] => 2014-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3352 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15037244 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11090392 [patent_doc_number] => 20160287360 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-10-06 [patent_title] => 'METHOD FOR DESIGNING ATTACHMENT ABUTMENTS FOR ATTACHING DENTURES TO THE MANDIBLE AND/OR MAXILLA' [patent_app_type] => utility [patent_app_number] => 15/035857 [patent_app_country] => US [patent_app_date] => 2014-11-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4890 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15035857 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10787170 [patent_doc_number] => 20160133326 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-05-12 [patent_title] => 'APPARATUSES AND METHODS FOR NON-VOLATILE MEMORY PROGRAMMING SCHEMES' [patent_app_type] => utility [patent_app_number] => 14/538477 [patent_app_country] => US [patent_app_date] => 2014-11-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5977 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14538477 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10597112 [patent_doc_number] => 09318206 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-04-19 [patent_title] => 'Selective word line erase in 3D non-volatile memory' [patent_app_type] => utility [patent_app_number] => 14/536923 [patent_app_country] => US [patent_app_date] => 2014-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 36 [patent_no_of_words] => 13256 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 265 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14536923 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10358350 [patent_doc_number] => 20150243355 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-08-27 [patent_title] => 'VARIABLE RESISTANCE MEMORY DEVICE AND RELATED PROGRAMMING METHOD DESIGNED TO REDUCE PEAK CURRENT' [patent_app_type] => utility [patent_app_number] => 14/532105 [patent_app_country] => US [patent_app_date] => 2014-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 5843 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14532105 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11745618 [patent_doc_number] => 20170199692 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-07-13 [patent_title] => 'SHARED BACKUP POWER SELF-REFRESH MODE' [patent_app_type] => utility [patent_app_number] => 15/324977 [patent_app_country] => US [patent_app_date] => 2014-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6357 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15324977 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11097246 [patent_doc_number] => 20160294215 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-10-06 [patent_title] => 'POWER CONTROL SYSTEM, POWER CONTROL METHOD, AND RECORDING MEDIUM' [patent_app_type] => utility [patent_app_number] => 15/033612 [patent_app_country] => US [patent_app_date] => 2014-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 12490 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15033612 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10597092 [patent_doc_number] => 09318185 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-04-19 [patent_title] => 'Memory module and memory system including the same' [patent_app_type] => utility [patent_app_number] => 14/517255 [patent_app_country] => US [patent_app_date] => 2014-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 23 [patent_no_of_words] => 13609 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14517255 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10617443 [patent_doc_number] => 09336890 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-05-10 [patent_title] => 'Simultaneous programming of many bits in flash memory' [patent_app_type] => utility [patent_app_number] => 14/517201 [patent_app_country] => US [patent_app_date] => 2014-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 14 [patent_no_of_words] => 6804 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14517201 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11042507 [patent_doc_number] => 20160239464 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-08-18 [patent_title] => 'Method and System for Tracking the Centre of a Peak from a plurality of Sample Points in an Optical System' [patent_app_type] => utility [patent_app_number] => 15/029716 [patent_app_country] => US [patent_app_date] => 2014-10-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5040 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15029716 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10752880 [patent_doc_number] => 20160099032 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-04-07 [patent_title] => 'BI-SYNCHRONOUS ELECTRONIC DEVICE AND FIFO MEMORY CIRCUIT WITH JUMP CANDIDATES AND RELATED METHODS' [patent_app_type] => utility [patent_app_number] => 14/508321 [patent_app_country] => US [patent_app_date] => 2014-10-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3486 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14508321 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11483093 [patent_doc_number] => 09589645 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-03-07 [patent_title] => 'Block refresh to adapt to new die trim settings' [patent_app_type] => utility [patent_app_number] => 14/507245 [patent_app_country] => US [patent_app_date] => 2014-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 7539 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14507245 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12249932 [patent_doc_number] => 09922715 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-03-20 [patent_title] => 'Non-volatile split gate memory device and a method of operating same' [patent_app_type] => utility [patent_app_number] => 14/506433 [patent_app_country] => US [patent_app_date] => 2014-10-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 21 [patent_no_of_words] => 5949 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 294 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14506433 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10747194 [patent_doc_number] => 20160093346 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-03-31 [patent_title] => 'VOLTAGE LEVEL SHIFTED SELF-CLOCKED WRITE ASSISTANCE' [patent_app_type] => utility [patent_app_number] => 14/499035 [patent_app_country] => US [patent_app_date] => 2014-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6514 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14499035 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10010450 [patent_doc_number] => 09053975 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-06-09 [patent_title] => 'Semicondutor integrated circuit device and system' [patent_app_type] => utility [patent_app_number] => 14/490461 [patent_app_country] => US [patent_app_date] => 2014-09-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 37 [patent_no_of_words] => 31678 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 317 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14490461 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14393487 [patent_doc_number] => 10310020 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-06-04 [patent_title] => Method, device and system for estimating the charge state of a battery [patent_app_type] => utility [patent_app_number] => 14/912582 [patent_app_country] => US [patent_app_date] => 2014-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 7634 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 260 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14912582 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11300386 [patent_doc_number] => 09508396 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-11-29 [patent_title] => 'Array structure of single-ploy nonvolatile memory' [patent_app_type] => utility [patent_app_number] => 14/471613 [patent_app_country] => US [patent_app_date] => 2014-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 19 [patent_no_of_words] => 8096 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 344 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14471613 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10589259 [patent_doc_number] => 09310869 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-04-12 [patent_title] => 'Memory storage device, memory control circuit unit and power supply method' [patent_app_type] => utility [patent_app_number] => 14/462569 [patent_app_country] => US [patent_app_date] => 2014-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 9529 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14462569 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11467052 [patent_doc_number] => 09583696 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-02-28 [patent_title] => 'Reference layer for perpendicular magnetic anisotropy magnetic tunnel junction' [patent_app_type] => utility [patent_app_number] => 14/460731 [patent_app_country] => US [patent_app_date] => 2014-08-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 10179 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14460731 [rel_patent_id] =>[rel_patent_doc_number] =>)