Search

Terri L. Filosi

Examiner (ID: 5593, Phone: (571)270-1988 , Office: P/2143 )

Most Active Art Unit
3644
Art Unit(s)
2143, 3762, 3644, 2178
Total Applications
473
Issued Applications
279
Pending Applications
39
Abandoned Applications
165

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 9900208 [patent_doc_number] => 20150055407 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-02-26 [patent_title] => 'SET AND RESET OPERATION IN PHASE CHANGE MEMORY AND ASSOCIATED TECHNIQUES AND CONFIGURATIONS' [patent_app_type] => utility [patent_app_number] => 14/010417 [patent_app_country] => US [patent_app_date] => 2013-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 7824 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14010417 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/010417
Set and reset operation in phase change memory and associated techniques and configurations Aug 25, 2013 Issued
Array ( [id] => 9196762 [patent_doc_number] => 20130336077 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-12-19 [patent_title] => 'SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR TESTING SAME' [patent_app_type] => utility [patent_app_number] => 13/972407 [patent_app_country] => US [patent_app_date] => 2013-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 9004 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13972407 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/972407
Semiconductor memory device and method for testing same Aug 20, 2013 Issued
Array ( [id] => 9395263 [patent_doc_number] => 20140092669 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-04-03 [patent_title] => 'NON-VOLATILE VARIABLE RESISTIVE ELEMENT, CONTROLLING DEVICE AND STORAGE DEVICE' [patent_app_type] => utility [patent_app_number] => 13/965733 [patent_app_country] => US [patent_app_date] => 2013-08-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 42 [patent_figures_cnt] => 42 [patent_no_of_words] => 13865 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13965733 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/965733
Non-volatile variable resistive element, controlling device and storage device Aug 12, 2013 Issued
Array ( [id] => 9447922 [patent_doc_number] => 20140119091 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-05-01 [patent_title] => 'BIT-LINE SENSE AMPLIFIER, SEMICONDUCTOR MEMORY DEVICE AND MEMORY SYSTEM INCLUDING THE SAME' [patent_app_type] => utility [patent_app_number] => 13/960617 [patent_app_country] => US [patent_app_date] => 2013-08-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 7263 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13960617 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/960617
Bit-line sense amplifier, semiconductor memory device and memory system including the same Aug 5, 2013 Issued
Array ( [id] => 10100148 [patent_doc_number] => 09136468 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-09-15 [patent_title] => 'Nonvolatile semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 13/959493 [patent_app_country] => US [patent_app_date] => 2013-08-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 29 [patent_no_of_words] => 10874 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13959493 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/959493
Nonvolatile semiconductor memory device Aug 4, 2013 Issued
Array ( [id] => 9173030 [patent_doc_number] => 20130315015 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-11-28 [patent_title] => 'SEMICONDUCTOR APPARATUS, METHOD FOR DELAYING SIGNAL THEREOF, STACKED SEMICONDUCTOR MEMORY APPARATUS, AND METHOD FOR GENERATING SIGNAL THEREOF' [patent_app_type] => utility [patent_app_number] => 13/957086 [patent_app_country] => US [patent_app_date] => 2013-08-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4764 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13957086 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/957086
Semiconductor apparatus, method for delaying signal thereof, stacked semiconductor memory apparatus, and method for generating signal thereof Jul 31, 2013 Issued
Array ( [id] => 11564465 [patent_doc_number] => 09627057 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-04-18 [patent_title] => 'Programming two-terminal memory cells with reduced program current' [patent_app_type] => utility [patent_app_number] => 13/954853 [patent_app_country] => US [patent_app_date] => 2013-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 10859 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 263 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13954853 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/954853
Programming two-terminal memory cells with reduced program current Jul 29, 2013 Issued
Array ( [id] => 9519721 [patent_doc_number] => 20140156213 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-06-05 [patent_title] => 'SEMICONDUCTOR MEMORY DEVICES AND METHODS OF TESTING OPEN FAILURES THEREOF' [patent_app_type] => utility [patent_app_number] => 13/845173 [patent_app_country] => US [patent_app_date] => 2013-03-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 8681 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13845173 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/845173
Semiconductor memory devices and methods of testing open failures thereof Mar 17, 2013 Issued
Array ( [id] => 8926732 [patent_doc_number] => 20130182492 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-07-18 [patent_title] => '10T SRAM CELL WITH NEAR DUAL PORT FUNCTIONALITY' [patent_app_type] => utility [patent_app_number] => 13/783874 [patent_app_country] => US [patent_app_date] => 2013-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7679 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13783874 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/783874
10T SRAM CELL WITH NEAR DUAL PORT FUNCTIONALITY Mar 3, 2013 Abandoned
Array ( [id] => 10889421 [patent_doc_number] => 08913423 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-12-16 [patent_title] => 'Reducing source loading effect in spin torque transfer magnetoresistive random access memory (STT-MRAM)' [patent_app_type] => utility [patent_app_number] => 13/772576 [patent_app_country] => US [patent_app_date] => 2013-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 9477 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13772576 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/772576
Reducing source loading effect in spin torque transfer magnetoresistive random access memory (STT-MRAM) Feb 20, 2013 Issued
Array ( [id] => 9329274 [patent_doc_number] => 20140056056 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-02-27 [patent_title] => 'METHOD FOR READING DATA FROM NONVOLATILE MEMORY ELEMENT, AND NONVOLATILE MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 14/111831 [patent_app_country] => US [patent_app_date] => 2013-02-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 18015 [patent_no_of_claims] => 42 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14111831 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/111831
METHOD FOR READING DATA FROM NONVOLATILE MEMORY ELEMENT, AND NONVOLATILE MEMORY DEVICE Feb 14, 2013 Abandoned
Array ( [id] => 8766262 [patent_doc_number] => 20130094299 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-04-18 [patent_title] => 'Complementary Reference Method for High Reliability Trap-Type Non-Volatile Memory' [patent_app_type] => utility [patent_app_number] => 13/692503 [patent_app_country] => US [patent_app_date] => 2012-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 5517 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13692503 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/692503
Complementary reference method for high reliability trap-type non-volatile memory Dec 2, 2012 Issued
Array ( [id] => 8766266 [patent_doc_number] => 20130094303 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-04-18 [patent_title] => 'Complementary Reference Method for High Reliability Trap-Type Non-Volatile Memory' [patent_app_type] => utility [patent_app_number] => 13/692497 [patent_app_country] => US [patent_app_date] => 2012-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 5515 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13692497 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/692497
Complementary Reference Method for High Reliability Trap-Type Non-Volatile Memory Dec 2, 2012 Abandoned
Array ( [id] => 10502288 [patent_doc_number] => 09230690 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-01-05 [patent_title] => 'Register file write ring oscillator' [patent_app_type] => utility [patent_app_number] => 13/670739 [patent_app_country] => US [patent_app_date] => 2012-11-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5286 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13670739 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/670739
Register file write ring oscillator Nov 6, 2012 Issued
Array ( [id] => 11770120 [patent_doc_number] => 09378805 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-06-28 [patent_title] => 'Stable memory source bias over temperature and method' [patent_app_type] => utility [patent_app_number] => 13/663939 [patent_app_country] => US [patent_app_date] => 2012-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 18 [patent_no_of_words] => 6086 [patent_no_of_claims] => 67 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 210 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13663939 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/663939
Stable memory source bias over temperature and method Oct 29, 2012 Issued
Array ( [id] => 9447981 [patent_doc_number] => 20140119150 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-05-01 [patent_title] => 'BIPOLAR LOGIC GATES ON MOS-BASED MEMORY CHIPS' [patent_app_type] => utility [patent_app_number] => 13/660851 [patent_app_country] => US [patent_app_date] => 2012-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 8824 [patent_no_of_claims] => 58 [patent_no_of_ind_claims] => 14 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13660851 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/660851
Bipolar logic gates on MOS-based memory chips Oct 24, 2012 Issued
Array ( [id] => 9434522 [patent_doc_number] => 20140112429 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-04-24 [patent_title] => 'Low Voltage Register File Cell Structure' [patent_app_type] => utility [patent_app_number] => 13/658115 [patent_app_country] => US [patent_app_date] => 2012-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2588 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13658115 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/658115
Low Voltage Register File Cell Structure Oct 22, 2012 Abandoned
Array ( [id] => 9784312 [patent_doc_number] => 20140301132 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-10-09 [patent_title] => 'STORAGE CONTROL DEVICE, STORAGE DEVICE, INFORMATION PROCESSING SYSTEM, AND PROCESSING METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 14/364645 [patent_app_country] => US [patent_app_date] => 2012-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 10455 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14364645 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/364645
STORAGE CONTROL DEVICE, STORAGE DEVICE, INFORMATION PROCESSING SYSTEM, AND PROCESSING METHOD THEREOF Oct 18, 2012 Abandoned
Array ( [id] => 8696173 [patent_doc_number] => 20130058182 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-03-07 [patent_title] => 'Method and Apparatus for Programming an Anti-Fuse Element in a High-Voltage Integrated Circuit' [patent_app_type] => utility [patent_app_number] => 13/656066 [patent_app_country] => US [patent_app_date] => 2012-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4149 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13656066 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/656066
Method and apparatus for programming an anti-fuse element in a high-voltage integrated circuit Oct 18, 2012 Issued
Array ( [id] => 8778780 [patent_doc_number] => 20130100755 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-04-25 [patent_title] => 'SEMICONDUCTOR MEMORY DEVICE IMPLEMENTING COMPREHENSIVE PARTIAL ARRAY SELF REFRESH SCHEME' [patent_app_type] => utility [patent_app_number] => 13/653799 [patent_app_country] => US [patent_app_date] => 2012-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 7695 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13653799 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/653799
SEMICONDUCTOR MEMORY DEVICE IMPLEMENTING COMPREHENSIVE PARTIAL ARRAY SELF REFRESH SCHEME Oct 16, 2012 Abandoned
Menu