Terri L. Filosi

Array ( [id] => 8250880 [patent_doc_number] => 20120155200 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-06-21 [patent_title] => 'MEMORY DEVICE, MEMORY SYSTEM INCLUDING THE SAME, AND CONTROL METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 13/299497 [patent_app_country] => US [patent_app_date] => 2011-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5765 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0155/20120155200.pdf [firstpage_image] =>[orig_patent_app_number] => 13299497 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9819353 [patent_doc_number] => 08929148 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-01-06 [patent_title] => 'Semiconductor memory device having improved erase characteristic of memory cells and erase method thereof' [patent_app_type] => utility [patent_app_number] => 13/293391 [patent_app_country] => US [patent_app_date] => 2011-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 13 [patent_no_of_words] => 5359 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 234 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13293391 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8182535 [patent_doc_number] => 20120113707 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-05-10 [patent_title] => 'SEMICONDUCTOR MEMORY DEVICE AND DRIVING METHOD OF SEMICONDUCTOR MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 13/288089 [patent_app_country] => US [patent_app_date] => 2011-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 12046 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0113/20120113707.pdf [firstpage_image] =>[orig_patent_app_number] => 13288089 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10871858 [patent_doc_number] => 08897070 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-11-25 [patent_title] => 'Selective word line erase in 3D non-volatile memory' [patent_app_type] => utility [patent_app_number] => 13/287343 [patent_app_country] => US [patent_app_date] => 2011-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 36 [patent_no_of_words] => 13210 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 344 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13287343 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9764113 [patent_doc_number] => 08848450 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-09-30 [patent_title] => 'Method and apparatus for adjusting maximum verify time in nonvolatile memory device' [patent_app_type] => utility [patent_app_number] => 13/281793 [patent_app_country] => US [patent_app_date] => 2011-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 7479 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13281793 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10022057 [patent_doc_number] => 09064550 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-06-23 [patent_title] => 'Method and apparatus for word line suppression' [patent_app_type] => utility [patent_app_number] => 13/279375 [patent_app_country] => US [patent_app_date] => 2011-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4715 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13279375 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8766272 [patent_doc_number] => 20130094309 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-04-18 [patent_title] => 'TRACKING BIT CELL' [patent_app_type] => utility [patent_app_number] => 13/273705 [patent_app_country] => US [patent_app_date] => 2011-10-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 7524 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13273705 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10047181 [patent_doc_number] => 09087580 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-07-21 [patent_title] => 'Semiconductor memory having both volatile and non-volatile functionality including resistance change material and method of operating' [patent_app_type] => utility [patent_app_number] => 13/244812 [patent_app_country] => US [patent_app_date] => 2011-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 18 [patent_no_of_words] => 16040 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13244812 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8207678 [patent_doc_number] => 20120127791 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-05-24 [patent_title] => 'NONVOLATILE MEMORY DEVICE, MEMORY SYSTEM COMPRISING SAME, AND METHOD OF PROGRAMMING SAME' [patent_app_type] => utility [patent_app_number] => 13/236711 [patent_app_country] => US [patent_app_date] => 2011-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 7151 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0127/20120127791.pdf [firstpage_image] =>[orig_patent_app_number] => 13236711 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8322723 [patent_doc_number] => 20120195132 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-08-02 [patent_title] => 'SEMICONDUCTOR INTEGRATED CIRCUIT' [patent_app_type] => utility [patent_app_number] => 13/234373 [patent_app_country] => US [patent_app_date] => 2011-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4797 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13234373 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8428544 [patent_doc_number] => 20120250419 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-10-04 [patent_title] => 'METHOD OF CONTROLLING NONVOLATILE SEMICONDUCTOR MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 13/232259 [patent_app_country] => US [patent_app_date] => 2011-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6774 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13232259 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8263688 [patent_doc_number] => 20120163112 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-06-28 [patent_title] => 'SEMICONDUCTOR STORAGE SYSTEM CAPABLE OF SUPPRESSING PEAK CURRENT' [patent_app_type] => utility [patent_app_number] => 13/229999 [patent_app_country] => US [patent_app_date] => 2011-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 10821 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13229999 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7816603 [patent_doc_number] => 20120063223 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-03-15 [patent_title] => 'Most compact flotox-based combo NVM design without sacrificing EEPROM endurance cycles for 1-die data and code storage' [patent_app_type] => utility [patent_app_number] => 13/199785 [patent_app_country] => US [patent_app_date] => 2011-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 29 [patent_no_of_words] => 23390 [patent_no_of_claims] => 42 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0063/20120063223.pdf [firstpage_image] =>[orig_patent_app_number] => 13199785 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8415824 [patent_doc_number] => 20120243324 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-09-27 [patent_title] => 'NON-VOLATILE SEMICONDUCTOR STORAGE DEVICE' [patent_app_type] => utility [patent_app_number] => 13/223569 [patent_app_country] => US [patent_app_date] => 2011-09-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 8224 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13223569 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9979033 [patent_doc_number] => 09025356 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-05-05 [patent_title] => 'Fly-over conductor segments in integrated circuits with successive load devices along a signal path' [patent_app_type] => utility [patent_app_number] => 13/221081 [patent_app_country] => US [patent_app_date] => 2011-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6496 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13221081 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8334373 [patent_doc_number] => 20120201079 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-08-09 [patent_title] => 'SEMICONDUCTOR MEMORY DEVICE IN WHICH CAPACITANCE BETWEEN BIT LINES IS REDUCED, AND METHOD OF MANUFACTURING THE SAME' [patent_app_type] => utility [patent_app_number] => 13/218723 [patent_app_country] => US [patent_app_date] => 2011-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 11020 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13218723 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 8193783 [patent_doc_number] => 20120119806 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-05-17 [patent_title] => 'DATA OUTPUT CIRCUIT' [patent_app_type] => utility [patent_app_number] => 13/217412 [patent_app_country] => US [patent_app_date] => 2011-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 2717 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0119/20120119806.pdf [firstpage_image] =>[orig_patent_app_number] => 13217412 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9764131 [patent_doc_number] => 08848468 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-09-30 [patent_title] => 'Semiconductor device and control method thereof for permitting the reception of data according to a control signal' [patent_app_type] => utility [patent_app_number] => 13/213913 [patent_app_country] => US [patent_app_date] => 2011-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 18 [patent_no_of_words] => 6972 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13213913 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9203945 [patent_doc_number] => 20140003122 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-01-02 [patent_title] => 'SEMICONDUCTOR MEMORY STRUCTURE AND CONTROL METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 13/501833 [patent_app_country] => US [patent_app_date] => 2011-08-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3289 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13501833 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9945880 [patent_doc_number] => 08995196 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-03-31 [patent_title] => 'Method of sorting a multi-bit per cell non-volatile memory and a multi-mode configuration method' [patent_app_type] => utility [patent_app_number] => 13/210195 [patent_app_country] => US [patent_app_date] => 2011-08-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 14 [patent_no_of_words] => 3559 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13210195 [rel_patent_id] =>[rel_patent_doc_number] =>)