Search

Terri L. Filosi

Examiner (ID: 5593, Phone: (571)270-1988 , Office: P/2143 )

Most Active Art Unit
3644
Art Unit(s)
2143, 3762, 3644, 2178
Total Applications
473
Issued Applications
279
Pending Applications
39
Abandoned Applications
165

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 8658280 [patent_doc_number] => 20130039109 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-02-14 [patent_title] => 'SELECTABLE MULTI-WAY COMPARATOR' [patent_app_type] => utility [patent_app_number] => 13/207749 [patent_app_country] => US [patent_app_date] => 2011-08-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 8570 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13207749 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/207749
Selectable multi-way comparator Aug 10, 2011 Issued
Array ( [id] => 8636207 [patent_doc_number] => 20130028010 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-01-31 [patent_title] => 'Fast MTJ Switching Write Circuit For MRAM Array' [patent_app_type] => utility [patent_app_number] => 13/193689 [patent_app_country] => US [patent_app_date] => 2011-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 9475 [patent_no_of_claims] => 39 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13193689 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/193689
Fast MTJ Switching Write Circuit For MRAM Array Jul 28, 2011 Abandoned
Array ( [id] => 8463844 [patent_doc_number] => 20120269012 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-10-25 [patent_title] => 'SEMICONDUCTOR INTEGRATED CIRCUIT AND METHOD FOR DRIVING THE SAME' [patent_app_type] => utility [patent_app_number] => 13/190925 [patent_app_country] => US [patent_app_date] => 2011-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4112 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13190925 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/190925
SEMICONDUCTOR INTEGRATED CIRCUIT AND METHOD FOR DRIVING THE SAME Jul 25, 2011 Abandoned
Array ( [id] => 9851663 [patent_doc_number] => 08953404 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-02-10 [patent_title] => 'Semiconductor device having an electrical fuse element' [patent_app_type] => utility [patent_app_number] => 13/185127 [patent_app_country] => US [patent_app_date] => 2011-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 16 [patent_no_of_words] => 5893 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13185127 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/185127
Semiconductor device having an electrical fuse element Jul 17, 2011 Issued
Array ( [id] => 9583896 [patent_doc_number] => 08773901 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-07-08 [patent_title] => 'Nonvolatile memory device preventing shift in threshold voltage of erase cell and program method thereof' [patent_app_type] => utility [patent_app_number] => 13/178985 [patent_app_country] => US [patent_app_date] => 2011-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 3228 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13178985 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/178985
Nonvolatile memory device preventing shift in threshold voltage of erase cell and program method thereof Jul 7, 2011 Issued
Array ( [id] => 11452981 [patent_doc_number] => 09576630 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-02-21 [patent_title] => 'Memory devices and methods having multiple address accesses in same cycle' [patent_app_type] => utility [patent_app_number] => 13/179307 [patent_app_country] => US [patent_app_date] => 2011-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 28 [patent_no_of_words] => 6383 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 231 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13179307 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/179307
Memory devices and methods having multiple address accesses in same cycle Jul 7, 2011 Issued
Array ( [id] => 8588506 [patent_doc_number] => 20130007327 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-01-03 [patent_title] => 'USING POWER DIVIDING MATCHING NODES TO OPTIMIZE INTERCONNECTS' [patent_app_type] => utility [patent_app_number] => 13/173959 [patent_app_country] => US [patent_app_date] => 2011-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2514 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13173959 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/173959
USING POWER DIVIDING MATCHING NODES TO OPTIMIZE INTERCONNECTS Jun 29, 2011 Abandoned
Array ( [id] => 10889412 [patent_doc_number] => 08913414 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-12-16 [patent_title] => 'Semiconductor apparatus and semiconductor system for outputting internal information according to various mode and method for outputting internal information thereof' [patent_app_type] => utility [patent_app_number] => 13/171815 [patent_app_country] => US [patent_app_date] => 2011-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 5185 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13171815 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/171815
Semiconductor apparatus and semiconductor system for outputting internal information according to various mode and method for outputting internal information thereof Jun 28, 2011 Issued
Array ( [id] => 9824800 [patent_doc_number] => 08934293 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2015-01-13 [patent_title] => 'Means and method for operating a resistive array' [patent_app_type] => utility [patent_app_number] => 13/135235 [patent_app_country] => US [patent_app_date] => 2011-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 7490 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13135235 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/135235
Means and method for operating a resistive array Jun 28, 2011 Issued
Array ( [id] => 8321834 [patent_doc_number] => 20120194243 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-08-02 [patent_title] => 'SEMICONDUCTOR APPARATUS AND REPAIR METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 13/168241 [patent_app_country] => US [patent_app_date] => 2011-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 9646 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13168241 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/168241
Semiconductor apparatus transmitting fuse information and repair method thereof Jun 23, 2011 Issued
Array ( [id] => 9779652 [patent_doc_number] => 08854866 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-10-07 [patent_title] => 'Identification circuit and method for generating an identification bit' [patent_app_type] => utility [patent_app_number] => 13/163131 [patent_app_country] => US [patent_app_date] => 2011-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4244 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13163131 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/163131
Identification circuit and method for generating an identification bit Jun 16, 2011 Issued
Array ( [id] => 8508160 [patent_doc_number] => 20120307568 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-12-06 [patent_title] => 'TECHNIQUES FOR PROVIDING A SEMICONDUCTOR MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 13/153707 [patent_app_country] => US [patent_app_date] => 2011-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 12001 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13153707 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/153707
Semiconductor memory device and method for biasing same Jun 5, 2011 Issued
Array ( [id] => 8506613 [patent_doc_number] => 20120306021 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-12-06 [patent_title] => 'SEMICONDUCTOR DEVICE AND METHOD OF FABRICATION' [patent_app_type] => utility [patent_app_number] => 13/153179 [patent_app_country] => US [patent_app_date] => 2011-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3379 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13153179 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/153179
SEMICONDUCTOR DEVICE AND METHOD OF FABRICATION Jun 2, 2011 Abandoned
Array ( [id] => 8508137 [patent_doc_number] => 20120307545 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-12-06 [patent_title] => 'Interleaved Bit Line Architecture for 2T2C Ferroelectric Memories' [patent_app_type] => utility [patent_app_number] => 13/150885 [patent_app_country] => US [patent_app_date] => 2011-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 8546 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13150885 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/150885
Interleaved Bit Line Architecture for 2T2C Ferroelectric Memories May 31, 2011 Abandoned
Array ( [id] => 8511993 [patent_doc_number] => 20120311401 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-12-06 [patent_title] => 'MULTIPORT MEMORY ELEMENT CIRCUITRY' [patent_app_type] => utility [patent_app_number] => 13/149249 [patent_app_country] => US [patent_app_date] => 2011-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7607 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13149249 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/149249
Multiport memory element circuitry May 30, 2011 Issued
Array ( [id] => 7585557 [patent_doc_number] => 20110280067 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-11-17 [patent_title] => 'NONVOLATILE MEMORY DEVICE, MEMORY SYSTEM HAVING THE SAME AND PROGRAMMING METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 13/108391 [patent_app_country] => US [patent_app_date] => 2011-05-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 9075 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0280/20110280067.pdf [firstpage_image] =>[orig_patent_app_number] => 13108391 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/108391
Nonvolatile memory device having selectable sensing modes, memory system having the same and programming method thereof May 15, 2011 Issued
Array ( [id] => 8440818 [patent_doc_number] => 20120257435 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-10-11 [patent_title] => 'NON-SALICIDE POLYSILICON FUSE' [patent_app_type] => utility [patent_app_number] => 13/107441 [patent_app_country] => US [patent_app_date] => 2011-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4841 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13107441 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/107441
Non-salicide polysilicon fuse May 12, 2011 Issued
Array ( [id] => 9377296 [patent_doc_number] => 08681566 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-03-25 [patent_title] => 'Apparatus and methods of driving signal for reducing the leakage current' [patent_app_type] => utility [patent_app_number] => 13/106321 [patent_app_country] => US [patent_app_date] => 2011-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5842 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13106321 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/106321
Apparatus and methods of driving signal for reducing the leakage current May 11, 2011 Issued
Array ( [id] => 9021883 [patent_doc_number] => 08531873 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-09-10 [patent_title] => 'Ultra low power SRAM cell circuit with a supply feedback loop for near and sub threshold operation' [patent_app_type] => utility [patent_app_number] => 13/103091 [patent_app_country] => US [patent_app_date] => 2011-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 4097 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 277 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13103091 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/103091
Ultra low power SRAM cell circuit with a supply feedback loop for near and sub threshold operation May 7, 2011 Issued
Array ( [id] => 7498176 [patent_doc_number] => 20110261616 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-10-27 [patent_title] => 'WRITE SCHEME IN PHASE CHANGE MEMORY' [patent_app_type] => utility [patent_app_number] => 13/093923 [patent_app_country] => US [patent_app_date] => 2011-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 33 [patent_figures_cnt] => 33 [patent_no_of_words] => 9861 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0261/20110261616.pdf [firstpage_image] =>[orig_patent_app_number] => 13093923 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/093923
WRITE SCHEME IN PHASE CHANGE MEMORY Apr 25, 2011 Abandoned
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