Search

Terri L. Filosi

Examiner (ID: 5593, Phone: (571)270-1988 , Office: P/2143 )

Most Active Art Unit
3644
Art Unit(s)
2143, 3762, 3644, 2178
Total Applications
473
Issued Applications
279
Pending Applications
39
Abandoned Applications
165

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19116137 [patent_doc_number] => 20240127887 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-04-18 [patent_title] => STRUCTURE FOR MULTIPLE SENSE AMPLIFIERS OF MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/394835 [patent_app_country] => US [patent_app_date] => 2023-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7700 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18394835 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/394835
STRUCTURE FOR MULTIPLE SENSE AMPLIFIERS OF MEMORY DEVICE Dec 21, 2023 Pending
Array ( [id] => 19712375 [patent_doc_number] => 20250022517 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-16 [patent_title] => MEMORY DEVICE AND OPERATING METHOD OF THE MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/390456 [patent_app_country] => US [patent_app_date] => 2023-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8855 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 49 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18390456 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/390456
MEMORY DEVICE AND OPERATING METHOD OF THE MEMORY DEVICE Dec 19, 2023 Pending
Array ( [id] => 19085926 [patent_doc_number] => 20240112727 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-04-04 [patent_title] => INTERFACE OF A MEMORY CIRCUIT [patent_app_type] => utility [patent_app_number] => 18/535112 [patent_app_country] => US [patent_app_date] => 2023-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6224 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18535112 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/535112
Interface of a memory circuit Dec 10, 2023 Issued
Array ( [id] => 20345794 [patent_doc_number] => 12469529 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-11-11 [patent_title] => Buffer device with low-latency skid mode for data freshness [patent_app_type] => utility [patent_app_number] => 18/531543 [patent_app_country] => US [patent_app_date] => 2023-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 0 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18531543 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/531543
Buffer device with low-latency skid mode for data freshness Dec 5, 2023 Issued
Array ( [id] => 19842515 [patent_doc_number] => 12254914 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-03-18 [patent_title] => Memory cell with access device and memory capacitor structures [patent_app_type] => utility [patent_app_number] => 18/530182 [patent_app_country] => US [patent_app_date] => 2023-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 39 [patent_figures_cnt] => 39 [patent_no_of_words] => 55570 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18530182 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/530182
Memory cell with access device and memory capacitor structures Dec 4, 2023 Issued
Array ( [id] => 20495162 [patent_doc_number] => 12537038 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-01-27 [patent_title] => Column address generation circuit and semiconductor apparatus including the column address generation circuit [patent_app_type] => utility [patent_app_number] => 18/527702 [patent_app_country] => US [patent_app_date] => 2023-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 3732 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18527702 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/527702
Column address generation circuit and semiconductor apparatus including the column address generation circuit Dec 3, 2023 Issued
Array ( [id] => 19964644 [patent_doc_number] => 12334159 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-06-17 [patent_title] => Method and circuit for providing auxiliary power and storage device including the same [patent_app_type] => utility [patent_app_number] => 18/518651 [patent_app_country] => US [patent_app_date] => 2023-11-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 4466 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 326 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18518651 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/518651
Method and circuit for providing auxiliary power and storage device including the same Nov 23, 2023 Issued
Array ( [id] => 20037930 [patent_doc_number] => 20250176152 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-29 [patent_title] => Systems, Methods, and Devices for a Wordline or a Bitline Formed and Disposed Within a Backside Metal Layer [patent_app_type] => utility [patent_app_number] => 18/518795 [patent_app_country] => US [patent_app_date] => 2023-11-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2306 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 31 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18518795 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/518795
Systems, Methods, and Devices for a Wordline or a Bitline Formed and Disposed Within a Backside Metal Layer Nov 23, 2023 Pending
Array ( [id] => 20036036 [patent_doc_number] => 20250174258 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-29 [patent_title] => PHYSICAL LAYER CIRCUIT, WRITE LEVELING TRAINING CIRCUIT AND METHOD FOR CALIBRATING ACCESS CONTROL SIGNAL TRANSMITTED TO MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/518575 [patent_app_country] => US [patent_app_date] => 2023-11-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1154 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18518575 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/518575
Physical layer circuit, write leveling training circuit and method for calibrating access control signal transmitted to memory device Nov 22, 2023 Issued
Array ( [id] => 19285370 [patent_doc_number] => 20240221847 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-04 [patent_title] => NON-VOLATILE MEMORY INCLUDING JUDGMENT MEMORY CELL STRINGS AND OPERATING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/518444 [patent_app_country] => US [patent_app_date] => 2023-11-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4814 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18518444 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/518444
Non-volatile memory including judgment memory cell strings and operating method thereof Nov 22, 2023 Issued
Array ( [id] => 20441310 [patent_doc_number] => 12512150 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-12-30 [patent_title] => Memory device with global and local latches [patent_app_type] => utility [patent_app_number] => 18/516641 [patent_app_country] => US [patent_app_date] => 2023-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 1210 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18516641 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/516641
Memory device with global and local latches Nov 20, 2023 Issued
Array ( [id] => 19191116 [patent_doc_number] => 20240170029 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-23 [patent_title] => MEMORY DEVICE HEATING IN COLD ENVIRONMENTS [patent_app_type] => utility [patent_app_number] => 18/516769 [patent_app_country] => US [patent_app_date] => 2023-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13732 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18516769 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/516769
MEMORY DEVICE HEATING IN COLD ENVIRONMENTS Nov 20, 2023 Pending
Array ( [id] => 19191131 [patent_doc_number] => 20240170044 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-23 [patent_title] => POWER HOLD-OFF CIRCUIT [patent_app_type] => utility [patent_app_number] => 18/511473 [patent_app_country] => US [patent_app_date] => 2023-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8263 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18511473 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/511473
Power hold-off circuit Nov 15, 2023 Issued
Array ( [id] => 20469220 [patent_doc_number] => 12525262 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-01-13 [patent_title] => Power hold-off circuit [patent_app_type] => utility [patent_app_number] => 18/511479 [patent_app_country] => US [patent_app_date] => 2023-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2560 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18511479 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/511479
Power hold-off circuit Nov 15, 2023 Issued
Array ( [id] => 19175861 [patent_doc_number] => 20240161835 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-16 [patent_title] => SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 18/503258 [patent_app_country] => US [patent_app_date] => 2023-11-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7553 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18503258 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/503258
SEMICONDUCTOR DEVICE Nov 6, 2023 Pending
Array ( [id] => 19175846 [patent_doc_number] => 20240161820 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-16 [patent_title] => METHOD AND DEVICE FOR OPERATING A MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/503479 [patent_app_country] => US [patent_app_date] => 2023-11-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6415 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18503479 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/503479
METHOD AND DEVICE FOR OPERATING A MEMORY DEVICE Nov 6, 2023 Pending
Array ( [id] => 20344603 [patent_doc_number] => 12468332 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-11-11 [patent_title] => Enhanced chip select signal training [patent_app_type] => utility [patent_app_number] => 18/499048 [patent_app_country] => US [patent_app_date] => 2023-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 11256 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 190 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18499048 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/499048
Enhanced chip select signal training Oct 30, 2023 Issued
Array ( [id] => 19252485 [patent_doc_number] => 20240203482 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-20 [patent_title] => Negative Pull-Down Voltage in a Sense Amplifier [patent_app_type] => utility [patent_app_number] => 18/494463 [patent_app_country] => US [patent_app_date] => 2023-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8265 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18494463 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/494463
Negative Pull-Down Voltage in a Sense Amplifier Oct 24, 2023 Pending
Array ( [id] => 19696069 [patent_doc_number] => 20250014614 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-09 [patent_title] => SEMICONDUCTOR MEMORY DEVICES WITH FLYING BIT LINES AND METHODS OF MANUFACTURING THEREOF [patent_app_type] => utility [patent_app_number] => 18/490922 [patent_app_country] => US [patent_app_date] => 2023-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12397 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 189 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18490922 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/490922
SEMICONDUCTOR MEMORY DEVICES WITH FLYING BIT LINES AND METHODS OF MANUFACTURING THEREOF Oct 19, 2023 Pending
Array ( [id] => 18942292 [patent_doc_number] => 20240037431 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-01 [patent_title] => CONSTRUCTING AND PROGRAMMING QUANTUM HARDWARE FOR ROBUST QUANTUM ANNEALING PROCESSES [patent_app_type] => utility [patent_app_number] => 18/484233 [patent_app_country] => US [patent_app_date] => 2023-10-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6601 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18484233 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/484233
Constructing and programming quantum hardware for robust quantum annealing processes Oct 9, 2023 Issued
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