Search

Terri L. Filosi

Examiner (ID: 5593, Phone: (571)270-1988 , Office: P/2143 )

Most Active Art Unit
3644
Art Unit(s)
2143, 3762, 3644, 2178
Total Applications
473
Issued Applications
279
Pending Applications
39
Abandoned Applications
165

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 9168192 [patent_doc_number] => 08593876 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-11-26 [patent_title] => 'Sensing scheme in a memory device' [patent_app_type] => utility [patent_app_number] => 13/085611 [patent_app_country] => US [patent_app_date] => 2011-04-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 6028 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13085611 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/085611
Sensing scheme in a memory device Apr 12, 2011 Issued
Array ( [id] => 5957725 [patent_doc_number] => 20110182112 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-07-28 [patent_title] => '10T SRAM Cell with Near Dual Port Functionality' [patent_app_type] => utility [patent_app_number] => 13/080373 [patent_app_country] => US [patent_app_date] => 2011-04-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7652 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0182/20110182112.pdf [firstpage_image] =>[orig_patent_app_number] => 13080373 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/080373
10T SRAM cell with near dual port functionality Apr 4, 2011 Issued
Array ( [id] => 10859193 [patent_doc_number] => 08885399 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-11-11 [patent_title] => 'Phase change memory (PCM) architecture and a method for writing into PCM architecture' [patent_app_type] => utility [patent_app_number] => 13/075037 [patent_app_country] => US [patent_app_date] => 2011-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 6385 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 209 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13075037 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/075037
Phase change memory (PCM) architecture and a method for writing into PCM architecture Mar 28, 2011 Issued
Array ( [id] => 7585560 [patent_doc_number] => 20110280070 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-11-17 [patent_title] => 'NONVOLATILE MEMORY DEVICE, SYSTEM COMPRISING NONVOLATILE MEMORY DEVICE, AND READ OPERATION OF NONVOLATILE MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 13/073029 [patent_app_country] => US [patent_app_date] => 2011-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 5438 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0280/20110280070.pdf [firstpage_image] =>[orig_patent_app_number] => 13073029 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/073029
NONVOLATILE MEMORY DEVICE, SYSTEM COMPRISING NONVOLATILE MEMORY DEVICE, AND READ OPERATION OF NONVOLATILE MEMORY DEVICE Mar 27, 2011 Abandoned
Array ( [id] => 8404569 [patent_doc_number] => 20120236624 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-09-20 [patent_title] => 'Balanced Method for Programming Multi-Layer Cell Memories' [patent_app_type] => utility [patent_app_number] => 13/051885 [patent_app_country] => US [patent_app_date] => 2011-03-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 11394 [patent_no_of_claims] => 42 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13051885 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/051885
Balanced method for programming multi-layer cell memories Mar 17, 2011 Issued
Array ( [id] => 7655815 [patent_doc_number] => 20110305084 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-12-15 [patent_title] => 'NON-VOLATILE MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 13/050398 [patent_app_country] => US [patent_app_date] => 2011-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4126 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0305/20110305084.pdf [firstpage_image] =>[orig_patent_app_number] => 13050398 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/050398
NON-VOLATILE MEMORY DEVICE Mar 16, 2011 Abandoned
Array ( [id] => 7485079 [patent_doc_number] => 20110235407 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-09-29 [patent_title] => 'SEMICONDUCTOR MEMORY DEVICE AND A METHOD OF MANUFACTURING THE SAME' [patent_app_type] => utility [patent_app_number] => 13/043009 [patent_app_country] => US [patent_app_date] => 2011-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 30 [patent_no_of_words] => 23036 [patent_no_of_claims] => 51 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0235/20110235407.pdf [firstpage_image] =>[orig_patent_app_number] => 13043009 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/043009
SEMICONDUCTOR MEMORY DEVICE AND A METHOD OF MANUFACTURING THE SAME Mar 7, 2011 Abandoned
Array ( [id] => 8380782 [patent_doc_number] => 20120224410 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-09-06 [patent_title] => 'THREE DIMENSIONAL MEMORY SYSTEM WITH INTELLIGENT SELECT CIRCUIT' [patent_app_type] => utility [patent_app_number] => 13/039593 [patent_app_country] => US [patent_app_date] => 2011-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 13693 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13039593 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/039593
Three dimensional memory system with intelligent select circuit Mar 2, 2011 Issued
Array ( [id] => 6013200 [patent_doc_number] => 20110222334 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-09-15 [patent_title] => 'SPIN TRANSFER TORQUE MRAM, AND WRITE METHOD AND READ METHOD THEREFOR' [patent_app_type] => utility [patent_app_number] => 13/036127 [patent_app_country] => US [patent_app_date] => 2011-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5769 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0222/20110222334.pdf [firstpage_image] =>[orig_patent_app_number] => 13036127 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/036127
SPIN TRANSFER TORQUE MRAM, AND WRITE METHOD AND READ METHOD THEREFOR Feb 27, 2011 Abandoned
Array ( [id] => 9160132 [patent_doc_number] => 20130308409 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-11-21 [patent_title] => 'INTEGRATED CIRCUIT DEVICE, POWER MANAGEMENT MODULE AND METHOD FOR PROVIDING POWER MANAGEMENT' [patent_app_type] => utility [patent_app_number] => 13/983145 [patent_app_country] => US [patent_app_date] => 2011-02-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7273 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13983145 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/983145
Integrated circuit device, power management module and method for providing power management Feb 7, 2011 Issued
Array ( [id] => 7698009 [patent_doc_number] => 20110228581 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-09-22 [patent_title] => 'STACKED MEMORY DEVICE AND METHOD OF REPAIRING SAME' [patent_app_type] => utility [patent_app_number] => 13/015847 [patent_app_country] => US [patent_app_date] => 2011-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 6074 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0228/20110228581.pdf [firstpage_image] =>[orig_patent_app_number] => 13015847 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/015847
Stacked memory device and method of repairing same Jan 27, 2011 Issued
Array ( [id] => 8573207 [patent_doc_number] => 08339860 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-12-25 [patent_title] => 'Semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 13/011629 [patent_app_country] => US [patent_app_date] => 2011-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7009 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13011629 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/011629
Semiconductor memory device Jan 20, 2011 Issued
Array ( [id] => 5999291 [patent_doc_number] => 20110116321 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-05-19 [patent_title] => 'SEMICONDUCTOR DEVICE FOR PREVENTING ERRONEOUS WRITE TO MEMORY CELL IN SWITCHING OPERATIONAL MODE BETWEEN NORMAL MODE AND STANDBY MODE' [patent_app_type] => utility [patent_app_number] => 13/008448 [patent_app_country] => US [patent_app_date] => 2011-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 9449 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0116/20110116321.pdf [firstpage_image] =>[orig_patent_app_number] => 13008448 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/008448
Semiconductor device for preventing erroneous write to memory cell in switching operational mode between normal mode and standby mode Jan 17, 2011 Issued
Array ( [id] => 9010940 [patent_doc_number] => 08526251 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-09-03 [patent_title] => 'Semiconductor apparatus, method for delaying signal thereof, stacked semiconductor memory apparatus, and method for generating signal thereof' [patent_app_type] => utility [patent_app_number] => 12/970882 [patent_app_country] => US [patent_app_date] => 2010-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 4768 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12970882 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/970882
Semiconductor apparatus, method for delaying signal thereof, stacked semiconductor memory apparatus, and method for generating signal thereof Dec 15, 2010 Issued
Array ( [id] => 8761787 [patent_doc_number] => 08422317 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-04-16 [patent_title] => 'Self-powered detection device with a non-volatile memory' [patent_app_type] => utility [patent_app_number] => 12/945168 [patent_app_country] => US [patent_app_date] => 2010-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 20 [patent_no_of_words] => 10300 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 308 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12945168 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/945168
Self-powered detection device with a non-volatile memory Nov 11, 2010 Issued
Array ( [id] => 7560099 [patent_doc_number] => 20110273931 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-11-10 [patent_title] => 'METHODS OF OPERATING MEMORY CELL HAVING ASYMMETRIC BAND-GAP TUNNEL INSULATOR USING DIRECT TUNNELING' [patent_app_type] => utility [patent_app_number] => 12/941458 [patent_app_country] => US [patent_app_date] => 2010-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 15152 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0273/20110273931.pdf [firstpage_image] =>[orig_patent_app_number] => 12941458 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/941458
Methods of operating memory cell having asymmetric band-gap tunnel insulator using direct tunneling Nov 7, 2010 Issued
Array ( [id] => 8167457 [patent_doc_number] => 20120105126 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-05-03 [patent_title] => 'DEVICE AND METHOD FOR STORING AND RETRIEVING OR FOR INCREASING PERSISTENCE TIME IN MEMORY STORAGE FOR ONE OR MORE BINARY DIGITS THROUGH STOCHASTIC RESONANCE' [patent_app_type] => utility [patent_app_number] => 12/915669 [patent_app_country] => US [patent_app_date] => 2010-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4928 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0105/20120105126.pdf [firstpage_image] =>[orig_patent_app_number] => 12915669 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/915669
DEVICE AND METHOD FOR STORING AND RETRIEVING OR FOR INCREASING PERSISTENCE TIME IN MEMORY STORAGE FOR ONE OR MORE BINARY DIGITS THROUGH STOCHASTIC RESONANCE Oct 28, 2010 Abandoned
Array ( [id] => 6201109 [patent_doc_number] => 20110063895 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-03-17 [patent_title] => 'SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND SYSTEM' [patent_app_type] => utility [patent_app_number] => 12/855691 [patent_app_country] => US [patent_app_date] => 2010-08-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 31708 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0063/20110063895.pdf [firstpage_image] =>[orig_patent_app_number] => 12855691 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/855691
Semiconductor integrated circuit device and system Aug 11, 2010 Issued
Array ( [id] => 6197964 [patent_doc_number] => 20110029722 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-02-03 [patent_title] => 'ELECTRONIC CONTROL APPARATUS INCLUDING ELECTRICALLY REWRITABLE NON-VOLATILE MEMORY' [patent_app_type] => utility [patent_app_number] => 12/849199 [patent_app_country] => US [patent_app_date] => 2010-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3720 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0029/20110029722.pdf [firstpage_image] =>[orig_patent_app_number] => 12849199 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/849199
ELECTRONIC CONTROL APPARATUS INCLUDING ELECTRICALLY REWRITABLE NON-VOLATILE MEMORY Aug 2, 2010 Abandoned
Array ( [id] => 7752884 [patent_doc_number] => 20120026802 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-02-02 [patent_title] => 'MANAGED HYBRID MEMORY WITH ADAPTIVE POWER SUPPLY' [patent_app_type] => utility [patent_app_number] => 12/847807 [patent_app_country] => US [patent_app_date] => 2010-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4591 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0026/20120026802.pdf [firstpage_image] =>[orig_patent_app_number] => 12847807 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/847807
MANAGED HYBRID MEMORY WITH ADAPTIVE POWER SUPPLY Jul 29, 2010 Abandoned
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