Search

Terri L. Filosi

Examiner (ID: 5593, Phone: (571)270-1988 , Office: P/2143 )

Most Active Art Unit
3644
Art Unit(s)
2143, 3762, 3644, 2178
Total Applications
473
Issued Applications
279
Pending Applications
39
Abandoned Applications
165

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 6191178 [patent_doc_number] => 20110173462 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-07-14 [patent_title] => 'CONTROLLING AND STAGGERING OPERATIONS TO LIMIT CURRENT SPIKES' [patent_app_type] => utility [patent_app_number] => 12/843419 [patent_app_country] => US [patent_app_date] => 2010-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4620 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0173/20110173462.pdf [firstpage_image] =>[orig_patent_app_number] => 12843419 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/843419
CONTROLLING AND STAGGERING OPERATIONS TO LIMIT CURRENT SPIKES Jul 25, 2010 Abandoned
Array ( [id] => 10884025 [patent_doc_number] => 08908412 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-12-09 [patent_title] => 'Array architecture for reduced voltage, low power, single poly EEPROM' [patent_app_type] => utility [patent_app_number] => 12/804439 [patent_app_country] => US [patent_app_date] => 2010-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 14 [patent_no_of_words] => 4774 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12804439 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/804439
Array architecture for reduced voltage, low power, single poly EEPROM Jul 19, 2010 Issued
Array ( [id] => 6147845 [patent_doc_number] => 20110019476 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-01-27 [patent_title] => 'NONVOLATILE MEMORY DEVICE AND PROGRAMMING METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 12/829623 [patent_app_country] => US [patent_app_date] => 2010-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 7379 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0019/20110019476.pdf [firstpage_image] =>[orig_patent_app_number] => 12829623 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/829623
Programming a nonvolatile memory device using a bias voltage to a well of a memory block Jul 1, 2010 Issued
Array ( [id] => 6337670 [patent_doc_number] => 20100329036 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-12-30 [patent_title] => 'NONVOLATILE MEMORY DEVICE AND READING METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 12/826261 [patent_app_country] => US [patent_app_date] => 2010-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6016 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0329/20100329036.pdf [firstpage_image] =>[orig_patent_app_number] => 12826261 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/826261
Nonvolatile memory device and reading method to read first memory cell in accordance of data stored in second memory cell adjacent to first memory cell Jun 28, 2010 Issued
Array ( [id] => 6349967 [patent_doc_number] => 20100331045 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-12-30 [patent_title] => 'EEPROM MEMORY ARCHITECTURE OPTIMIZED FOR EMBEDDED MEMORIES' [patent_app_type] => utility [patent_app_number] => 12/823901 [patent_app_country] => US [patent_app_date] => 2010-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 7115 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0331/20100331045.pdf [firstpage_image] =>[orig_patent_app_number] => 12823901 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/823901
EEPROM memory architecture optimized for embedded memories Jun 24, 2010 Issued
Array ( [id] => 7485209 [patent_doc_number] => 20110235453 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-09-29 [patent_title] => 'FUSE CIRCUIT AND REPAIR CONTROL CIRCUIT USING THE SAME' [patent_app_type] => utility [patent_app_number] => 12/815899 [patent_app_country] => US [patent_app_date] => 2010-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6446 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0235/20110235453.pdf [firstpage_image] =>[orig_patent_app_number] => 12815899 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/815899
FUSE CIRCUIT AND REPAIR CONTROL CIRCUIT USING THE SAME Jun 14, 2010 Abandoned
Array ( [id] => 6588547 [patent_doc_number] => 20100322020 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-12-23 [patent_title] => 'Data Storage Systems and Methods Using Data Attribute-Based Data Transfer' [patent_app_type] => utility [patent_app_number] => 12/796125 [patent_app_country] => US [patent_app_date] => 2010-06-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 7198 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0322/20100322020.pdf [firstpage_image] =>[orig_patent_app_number] => 12796125 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/796125
Data storage systems and methods using data attribute-based data transfer Jun 7, 2010 Issued
Array ( [id] => 8944977 [patent_doc_number] => 08498160 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-07-30 [patent_title] => 'Nonvolatile memory device and related programming method using selective bit line precharging' [patent_app_type] => utility [patent_app_number] => 12/793007 [patent_app_country] => US [patent_app_date] => 2010-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 16 [patent_no_of_words] => 8266 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12793007 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/793007
Nonvolatile memory device and related programming method using selective bit line precharging Jun 2, 2010 Issued
Array ( [id] => 6289640 [patent_doc_number] => 20100238738 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-09-23 [patent_title] => 'EEPROM Having Single Gate Structure and Method of Operating the Same' [patent_app_type] => utility [patent_app_number] => 12/787629 [patent_app_country] => US [patent_app_date] => 2010-05-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4429 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0238/20100238738.pdf [firstpage_image] =>[orig_patent_app_number] => 12787629 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/787629
EEPROM having single gate structure and method of operating the same May 25, 2010 Issued
Array ( [id] => 8691566 [patent_doc_number] => 08391097 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-03-05 [patent_title] => 'Memory word-line driver having reduced power consumption' [patent_app_type] => utility [patent_app_number] => 12/786791 [patent_app_country] => US [patent_app_date] => 2010-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2916 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12786791 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/786791
Memory word-line driver having reduced power consumption May 24, 2010 Issued
Array ( [id] => 7566208 [patent_doc_number] => 20110286271 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-11-24 [patent_title] => 'MEMORY SYSTEMS AND METHODS FOR READING DATA STORED IN A MEMORY CELL OF A MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 12/784621 [patent_app_country] => US [patent_app_date] => 2010-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 28 [patent_no_of_words] => 6304 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0286/20110286271.pdf [firstpage_image] =>[orig_patent_app_number] => 12784621 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/784621
MEMORY SYSTEMS AND METHODS FOR READING DATA STORED IN A MEMORY CELL OF A MEMORY DEVICE May 20, 2010 Abandoned
Array ( [id] => 6147795 [patent_doc_number] => 20110019460 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-01-27 [patent_title] => 'MEMORY CIRCUITS, SYSTEMS, AND FABRICATION METHODS THEREOF' [patent_app_type] => utility [patent_app_number] => 12/784133 [patent_app_country] => US [patent_app_date] => 2010-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4795 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0019/20110019460.pdf [firstpage_image] =>[orig_patent_app_number] => 12784133 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/784133
Memory circuit having memory cells with common source/drain region electrically isolated from all bit lines, system, and fabrication method thereof May 19, 2010 Issued
Array ( [id] => 6259226 [patent_doc_number] => 20100296332 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-11-25 [patent_title] => 'SRAM Cell for Single Sided Write' [patent_app_type] => utility [patent_app_number] => 12/782927 [patent_app_country] => US [patent_app_date] => 2010-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 8098 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0296/20100296332.pdf [firstpage_image] =>[orig_patent_app_number] => 12782927 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/782927
SRAM cell for single sided write May 18, 2010 Issued
Array ( [id] => 9274667 [patent_doc_number] => 08638609 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-01-28 [patent_title] => 'Partial local self boosting for NAND' [patent_app_type] => utility [patent_app_number] => 12/783351 [patent_app_country] => US [patent_app_date] => 2010-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 6391 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12783351 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/783351
Partial local self boosting for NAND May 18, 2010 Issued
Array ( [id] => 7584661 [patent_doc_number] => 20110279171 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-11-17 [patent_title] => 'ELECTRICALLY PROGRAMMABLE FUSE CONTROLLER FOR INTEGRATED CIRCUIT IDENTIFICATION, METHOD OF OPERATION THEREOF AND INTEGRATED CIRCUIT INCORPORATING THE SAME' [patent_app_type] => utility [patent_app_number] => 12/778305 [patent_app_country] => US [patent_app_date] => 2010-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2211 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0279/20110279171.pdf [firstpage_image] =>[orig_patent_app_number] => 12778305 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/778305
ELECTRICALLY PROGRAMMABLE FUSE CONTROLLER FOR INTEGRATED CIRCUIT IDENTIFICATION, METHOD OF OPERATION THEREOF AND INTEGRATED CIRCUIT INCORPORATING THE SAME May 11, 2010 Abandoned
Array ( [id] => 8529244 [patent_doc_number] => 08305826 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-11-06 [patent_title] => 'Method and apparatus for programming an anti-fuse element in a high-voltage integrated circuit' [patent_app_type] => utility [patent_app_number] => 12/800095 [patent_app_country] => US [patent_app_date] => 2010-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4124 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 222 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12800095 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/800095
Method and apparatus for programming an anti-fuse element in a high-voltage integrated circuit May 6, 2010 Issued
Array ( [id] => 5974536 [patent_doc_number] => 20110069570 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-03-24 [patent_title] => 'MEMORY CIRCUITS AND METHOD FOR ACCESSING DATA OF THE MEMORY CIRCUITS' [patent_app_type] => utility [patent_app_number] => 12/767979 [patent_app_country] => US [patent_app_date] => 2010-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3599 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0069/20110069570.pdf [firstpage_image] =>[orig_patent_app_number] => 12767979 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/767979
Memory circuit with switch between sense amplifier and data line and method for operating the same Apr 26, 2010 Issued
Array ( [id] => 9128678 [patent_doc_number] => 08576634 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-11-05 [patent_title] => 'Semiconductor device comprising a memory cell group having a gate width larger than a second memory cell group' [patent_app_type] => utility [patent_app_number] => 12/764090 [patent_app_country] => US [patent_app_date] => 2010-04-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 37 [patent_no_of_words] => 10279 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 217 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12764090 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/764090
Semiconductor device comprising a memory cell group having a gate width larger than a second memory cell group Apr 19, 2010 Issued
Array ( [id] => 6537309 [patent_doc_number] => 20100232210 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-09-16 [patent_title] => 'SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 12/723349 [patent_app_country] => US [patent_app_date] => 2010-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 7275 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0232/20100232210.pdf [firstpage_image] =>[orig_patent_app_number] => 12723349 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/723349
SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF Mar 11, 2010 Abandoned
Array ( [id] => 6491644 [patent_doc_number] => 20100214836 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-08-26 [patent_title] => 'Semiconductor storage apparatus' [patent_app_type] => utility [patent_app_number] => 12/656999 [patent_app_country] => US [patent_app_date] => 2010-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7755 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0214/20100214836.pdf [firstpage_image] =>[orig_patent_app_number] => 12656999 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/656999
Semiconductor storage apparatus including a pump circuit for the active mode and the standby mode Feb 22, 2010 Issued
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