Search

Terri L. Filosi

Examiner (ID: 5593, Phone: (571)270-1988 , Office: P/2143 )

Most Active Art Unit
3644
Art Unit(s)
2143, 3762, 3644, 2178
Total Applications
473
Issued Applications
279
Pending Applications
39
Abandoned Applications
165

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 6530538 [patent_doc_number] => 20100124128 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-05-20 [patent_title] => 'NAND FLASH MEMORY' [patent_app_type] => utility [patent_app_number] => 12/556219 [patent_app_country] => US [patent_app_date] => 2009-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5695 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0124/20100124128.pdf [firstpage_image] =>[orig_patent_app_number] => 12556219 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/556219
NAND FLASH MEMORY Sep 8, 2009 Abandoned
Array ( [id] => 6589086 [patent_doc_number] => 20100097842 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-04-22 [patent_title] => 'RESISTANCE VARIABLE MEMORY DEVICE PROGRAMMING MULTI-BIT DATA' [patent_app_type] => utility [patent_app_number] => 12/555831 [patent_app_country] => US [patent_app_date] => 2009-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3176 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0097/20100097842.pdf [firstpage_image] =>[orig_patent_app_number] => 12555831 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/555831
RESISTANCE VARIABLE MEMORY DEVICE PROGRAMMING MULTI-BIT DATA Sep 8, 2009 Abandoned
Array ( [id] => 9609906 [patent_doc_number] => 08787086 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-07-22 [patent_title] => 'Inhibiting address transitions in unselected memory banks of solid state memory circuits' [patent_app_type] => utility [patent_app_number] => 12/551045 [patent_app_country] => US [patent_app_date] => 2009-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 23 [patent_no_of_words] => 13000 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 196 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12551045 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/551045
Inhibiting address transitions in unselected memory banks of solid state memory circuits Aug 30, 2009 Issued
Array ( [id] => 6023159 [patent_doc_number] => 20110051485 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-03-03 [patent_title] => 'CONTENT ADDRESSABLE MEMORY ARRAY WRITING' [patent_app_type] => utility [patent_app_number] => 12/549761 [patent_app_country] => US [patent_app_date] => 2009-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4776 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0051/20110051485.pdf [firstpage_image] =>[orig_patent_app_number] => 12549761 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/549761
CONTENT ADDRESSABLE MEMORY ARRAY WRITING Aug 27, 2009 Abandoned
Array ( [id] => 6023164 [patent_doc_number] => 20110051490 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-03-03 [patent_title] => 'ARRAY ARCHITECTURE AND OPERATION FOR MAGNETIC RACETRACK MEMORY' [patent_app_type] => utility [patent_app_number] => 12/548113 [patent_app_country] => US [patent_app_date] => 2009-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4827 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0051/20110051490.pdf [firstpage_image] =>[orig_patent_app_number] => 12548113 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/548113
Array architecture and operation for high density magnetic racetrack memory system Aug 25, 2009 Issued
Array ( [id] => 6023186 [patent_doc_number] => 20110051512 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-03-03 [patent_title] => '3D MEMORY DEVICES DECODING AND ROUTING SYSTEMS AND METHODS' [patent_app_type] => utility [patent_app_number] => 12/547337 [patent_app_country] => US [patent_app_date] => 2009-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4213 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0051/20110051512.pdf [firstpage_image] =>[orig_patent_app_number] => 12547337 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/547337
3D memory devices decoding and routing systems and methods Aug 24, 2009 Issued
Array ( [id] => 6565166 [patent_doc_number] => 20100046302 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-02-25 [patent_title] => 'Complementary Reference method for high reliability trap-type non-volatile memory' [patent_app_type] => utility [patent_app_number] => 12/583743 [patent_app_country] => US [patent_app_date] => 2009-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 5492 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0046/20100046302.pdf [firstpage_image] =>[orig_patent_app_number] => 12583743 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/583743
Complementary reference method for high reliability trap-type non-volatile memory Aug 24, 2009 Issued
Array ( [id] => 6069245 [patent_doc_number] => 20110044094 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-02-24 [patent_title] => '10T SRAM Cell with Near Dual Port Functionality' [patent_app_type] => utility [patent_app_number] => 12/546291 [patent_app_country] => US [patent_app_date] => 2009-08-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7632 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0044/20110044094.pdf [firstpage_image] =>[orig_patent_app_number] => 12546291 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/546291
10T SRAM cell with near dual port functionality Aug 23, 2009 Issued
Array ( [id] => 6530698 [patent_doc_number] => 20100124140 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-05-20 [patent_title] => 'POWER SUPPLY CIRCUIT AND NAND-TYPE FLASH MEMORY' [patent_app_type] => utility [patent_app_number] => 12/544349 [patent_app_country] => US [patent_app_date] => 2009-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5542 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0124/20100124140.pdf [firstpage_image] =>[orig_patent_app_number] => 12544349 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/544349
POWER SUPPLY CIRCUIT AND NAND-TYPE FLASH MEMORY Aug 19, 2009 Abandoned
Array ( [id] => 6564755 [patent_doc_number] => 20100046274 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-02-25 [patent_title] => 'RESISTANCE CHANGE MEMORY' [patent_app_type] => utility [patent_app_number] => 12/543793 [patent_app_country] => US [patent_app_date] => 2009-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 8879 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0046/20100046274.pdf [firstpage_image] =>[orig_patent_app_number] => 12543793 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/543793
Resistance change memory Aug 18, 2009 Issued
Array ( [id] => 6218954 [patent_doc_number] => 20100054049 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-03-04 [patent_title] => 'SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 12/543499 [patent_app_country] => US [patent_app_date] => 2009-08-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 10819 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0054/20100054049.pdf [firstpage_image] =>[orig_patent_app_number] => 12543499 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/543499
Semiconductor memory device with read/write margin control using back-gate bias Aug 17, 2009 Issued
Array ( [id] => 9047990 [patent_doc_number] => 08542546 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-09-24 [patent_title] => 'Semiconductor memory device and method for testing same' [patent_app_type] => utility [patent_app_number] => 12/512573 [patent_app_country] => US [patent_app_date] => 2009-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 9117 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12512573 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/512573
Semiconductor memory device and method for testing same Jul 29, 2009 Issued
Array ( [id] => 6262487 [patent_doc_number] => 20100030954 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-02-04 [patent_title] => 'INFORMATION PROCESSING SYSTEM AND SEMICONDUCTOR STORAGE DEVICE' [patent_app_type] => utility [patent_app_number] => 12/510633 [patent_app_country] => US [patent_app_date] => 2009-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 17004 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0030/20100030954.pdf [firstpage_image] =>[orig_patent_app_number] => 12510633 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/510633
Memory device with pin register to set input/output direction and bitwidth of data signals Jul 27, 2009 Issued
Array ( [id] => 6565003 [patent_doc_number] => 20100046290 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-02-25 [patent_title] => 'FLASH MEMORY DEVICE AND MEMORY SYSTEM' [patent_app_type] => utility [patent_app_number] => 12/509611 [patent_app_country] => US [patent_app_date] => 2009-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 11649 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0046/20100046290.pdf [firstpage_image] =>[orig_patent_app_number] => 12509611 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/509611
FLASH MEMORY DEVICE AND MEMORY SYSTEM Jul 26, 2009 Abandoned
Array ( [id] => 6368227 [patent_doc_number] => 20100080063 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-04-01 [patent_title] => 'NONVOLATILE SEMICONDUCTOR MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 12/504201 [patent_app_country] => US [patent_app_date] => 2009-07-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 7003 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0080/20100080063.pdf [firstpage_image] =>[orig_patent_app_number] => 12504201 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/504201
NONVOLATILE SEMICONDUCTOR MEMORY DEVICE Jul 15, 2009 Abandoned
Array ( [id] => 10611043 [patent_doc_number] => 09331086 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-05-03 [patent_title] => 'Integrated circuit with trimming' [patent_app_type] => utility [patent_app_number] => 13/055211 [patent_app_country] => US [patent_app_date] => 2009-07-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 4994 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 206 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13055211 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/055211
Integrated circuit with trimming Jul 13, 2009 Issued
Array ( [id] => 7551903 [patent_doc_number] => 08064240 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-11-22 [patent_title] => 'Semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 12/502929 [patent_app_country] => US [patent_app_date] => 2009-07-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 5020 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/064/08064240.pdf [firstpage_image] =>[orig_patent_app_number] => 12502929 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/502929
Semiconductor memory device Jul 13, 2009 Issued
Array ( [id] => 7980155 [patent_doc_number] => 08072831 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-12-06 [patent_title] => 'Fuse element reading circuit' [patent_app_type] => utility [patent_app_number] => 12/501877 [patent_app_country] => US [patent_app_date] => 2009-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 9360 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/072/08072831.pdf [firstpage_image] =>[orig_patent_app_number] => 12501877 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/501877
Fuse element reading circuit Jul 12, 2009 Issued
Array ( [id] => 9985139 [patent_doc_number] => 09030867 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-05-12 [patent_title] => 'Bipolar CMOS select device for resistive sense memory' [patent_app_type] => utility [patent_app_number] => 12/502211 [patent_app_country] => US [patent_app_date] => 2009-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3322 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12502211 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/502211
Bipolar CMOS select device for resistive sense memory Jul 12, 2009 Issued
Array ( [id] => 6343075 [patent_doc_number] => 20100020618 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-01-28 [patent_title] => 'NON-VOLATILE MEMORY DEVICE AND MEMORY SYSTEM' [patent_app_type] => utility [patent_app_number] => 12/498477 [patent_app_country] => US [patent_app_date] => 2009-07-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 6391 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0020/20100020618.pdf [firstpage_image] =>[orig_patent_app_number] => 12498477 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/498477
Non-volatile memory device and memory system Jul 6, 2009 Issued
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