Search

Terry A. Wallace

Examiner (ID: 910, Phone: (571)272-2630 , Office: P/2916 )

Most Active Art Unit
2916
Art Unit(s)
2916, 2912, 2900, 2902
Total Applications
11456
Issued Applications
11361
Pending Applications
3
Abandoned Applications
90

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19305731 [patent_doc_number] => 20240234311 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-11 [patent_title] => REDUCED PITCH MEMORY SUBSYSTEM FOR MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/610267 [patent_app_country] => US [patent_app_date] => 2024-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14159 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18610267 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/610267
Reduced pitch memory subsystem for memory device Mar 19, 2024 Issued
Array ( [id] => 19285928 [patent_doc_number] => 20240222405 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-04 [patent_title] => IMAGE SENSORS WITH LIGHT CHANNELING REFLECTIVE LAYERS THEREIN [patent_app_type] => utility [patent_app_number] => 18/606413 [patent_app_country] => US [patent_app_date] => 2024-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5784 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 217 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18606413 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/606413
Image sensors with light channeling reflective layers therein Mar 14, 2024 Issued
Array ( [id] => 19161242 [patent_doc_number] => 20240153949 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-09 [patent_title] => INTEGRATED CHIP WITH IMPROVED LATCH-UP IMMUNITY [patent_app_type] => utility [patent_app_number] => 18/404234 [patent_app_country] => US [patent_app_date] => 2024-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 20051 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18404234 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/404234
INTEGRATED CHIP WITH IMPROVED LATCH-UP IMMUNITY Jan 3, 2024 Pending
Array ( [id] => 19118407 [patent_doc_number] => 20240130157 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-04-18 [patent_title] => LIGHT-EMITTING DEVICE AND METHOD FOR MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 18/393838 [patent_app_country] => US [patent_app_date] => 2023-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 20002 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18393838 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/393838
Light-emitting device and method for manufacturing the same Dec 21, 2023 Issued
Array ( [id] => 20205520 [patent_doc_number] => 12408315 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-09-02 [patent_title] => Flexible merge scheme for source/drain epitaxy regions [patent_app_type] => utility [patent_app_number] => 18/517275 [patent_app_country] => US [patent_app_date] => 2023-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 33 [patent_figures_cnt] => 33 [patent_no_of_words] => 1097 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18517275 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/517275
Flexible merge scheme for source/drain epitaxy regions Nov 21, 2023 Issued
Array ( [id] => 19038212 [patent_doc_number] => 20240088027 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-14 [patent_title] => INTEGRATED CIRCUIT WITH GUARD RING [patent_app_type] => utility [patent_app_number] => 18/508766 [patent_app_country] => US [patent_app_date] => 2023-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4165 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18508766 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/508766
Integrated circuit with guard ring Nov 13, 2023 Issued
Array ( [id] => 18905998 [patent_doc_number] => 20240021483 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-18 [patent_title] => SEMICONDUCTOR DEVICE, MANUFACTURING METHOD THEREOF, AND ELECTRONIC DEVICE INCLUDING THE DEVICE [patent_app_type] => utility [patent_app_number] => 18/477004 [patent_app_country] => US [patent_app_date] => 2023-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8947 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18477004 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/477004
SEMICONDUCTOR DEVICE, MANUFACTURING METHOD THEREOF, AND ELECTRONIC DEVICE INCLUDING THE DEVICE Sep 27, 2023 Abandoned
Array ( [id] => 19936881 [patent_doc_number] => 12310102 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-05-20 [patent_title] => Stacked vertical transport field-effect transistor logic gate structures with shared epitaxial layers [patent_app_type] => utility [patent_app_number] => 18/471718 [patent_app_country] => US [patent_app_date] => 2023-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 90 [patent_figures_cnt] => 91 [patent_no_of_words] => 22708 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 281 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18471718 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/471718
Stacked vertical transport field-effect transistor logic gate structures with shared epitaxial layers Sep 20, 2023 Issued
Array ( [id] => 18883075 [patent_doc_number] => 20240006444 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-04 [patent_title] => IMAGE SENSORS WITH LIGHT CHANNELING REFLECTIVE LAYERS THEREIN [patent_app_type] => utility [patent_app_number] => 18/468038 [patent_app_country] => US [patent_app_date] => 2023-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5770 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 210 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18468038 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/468038
IMAGE SENSORS WITH LIGHT CHANNELING REFLECTIVE LAYERS THEREIN Sep 14, 2023 Abandoned
Array ( [id] => 18882876 [patent_doc_number] => 20240006245 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-04 [patent_title] => WORK FUNCTION METAL PATTERNING FOR NANOSHEET CFETS [patent_app_type] => utility [patent_app_number] => 18/466301 [patent_app_country] => US [patent_app_date] => 2023-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6781 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18466301 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/466301
Work function metal patterning for nanosheet CFETs Sep 12, 2023 Issued
Array ( [id] => 18849113 [patent_doc_number] => 20230411517 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-21 [patent_title] => SEMICONDUCTOR DEVICES [patent_app_type] => utility [patent_app_number] => 18/239677 [patent_app_country] => US [patent_app_date] => 2023-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10596 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 204 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18239677 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/239677
Semiconductor devices Aug 28, 2023 Issued
Array ( [id] => 20216075 [patent_doc_number] => 12412729 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-09-09 [patent_title] => Atom probe tomography specimen preparation [patent_app_type] => utility [patent_app_number] => 18/448014 [patent_app_country] => US [patent_app_date] => 2023-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 0 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18448014 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/448014
Atom probe tomography specimen preparation Aug 9, 2023 Issued
Array ( [id] => 18789346 [patent_doc_number] => 20230378003 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-23 [patent_title] => METHOD OF MANUFACTURING SEMICONDUCTOR DEVICES [patent_app_type] => utility [patent_app_number] => 18/230367 [patent_app_country] => US [patent_app_date] => 2023-08-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7054 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18230367 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/230367
METHOD OF MANUFACTURING SEMICONDUCTOR DEVICES Aug 3, 2023 Pending
Array ( [id] => 19356991 [patent_doc_number] => 12057448 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-08-06 [patent_title] => Stacked semiconductor device having mirror-symmetric pattern [patent_app_type] => utility [patent_app_number] => 18/356545 [patent_app_country] => US [patent_app_date] => 2023-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 56 [patent_no_of_words] => 8725 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 191 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18356545 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/356545
Stacked semiconductor device having mirror-symmetric pattern Jul 20, 2023 Issued
Array ( [id] => 18759747 [patent_doc_number] => 20230363237 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-09 [patent_title] => DISPLAY DEVICE AND METHOD FOR MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 18/349943 [patent_app_country] => US [patent_app_date] => 2023-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10687 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18349943 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/349943
Display device and method for manufacturing the same Jul 9, 2023 Issued
Array ( [id] => 19356898 [patent_doc_number] => 12057354 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-08-06 [patent_title] => Trained neural network in in-situ monitoring during polishing and polishing system [patent_app_type] => utility [patent_app_number] => 18/200244 [patent_app_country] => US [patent_app_date] => 2023-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 7803 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 283 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18200244 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/200244
Trained neural network in in-situ monitoring during polishing and polishing system May 21, 2023 Issued
Array ( [id] => 18570444 [patent_doc_number] => 20230260781 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-08-17 [patent_title] => System And Method Of Forming A Porous Low-K Structure [patent_app_type] => utility [patent_app_number] => 18/305639 [patent_app_country] => US [patent_app_date] => 2023-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5454 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18305639 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/305639
System and method of forming a porous low-k structure Apr 23, 2023 Issued
Array ( [id] => 19765902 [patent_doc_number] => 12224203 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-02-11 [patent_title] => Air gap spacer formation for nano-scale semiconductor devices [patent_app_type] => utility [patent_app_number] => 18/132333 [patent_app_country] => US [patent_app_date] => 2023-04-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 21 [patent_no_of_words] => 11016 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18132333 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/132333
Air gap spacer formation for nano-scale semiconductor devices Apr 6, 2023 Issued
Array ( [id] => 18440198 [patent_doc_number] => 20230187493 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-15 [patent_title] => INTEGRATED CIRCUIT DEVICES INCLUDING A VERTICAL FIELD-EFFECT TRANSISTOR AND METHODS OF FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 18/166521 [patent_app_country] => US [patent_app_date] => 2023-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4760 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -3 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18166521 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/166521
Integrated circuit devices including a vertical field-effect transistor and methods of forming the same Feb 8, 2023 Issued
Array ( [id] => 18379712 [patent_doc_number] => 20230154801 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-05-18 [patent_title] => CMOS TOP SOURCE/DRAIN REGION DOPING AND EPITAXIAL GROWTH FOR A VERTICAL FIELD EFFECT TRANSISTOR [patent_app_type] => utility [patent_app_number] => 18/093932 [patent_app_country] => US [patent_app_date] => 2023-01-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6186 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18093932 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/093932
CMOS top source/drain region doping and epitaxial growth for a vertical field effect transistor Jan 5, 2023 Issued
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