Terry A Wallace
Examiner (ID: 10896, Phone: (571)272-2630 , Office: P/2916 )
Most Active Art Unit | 2916 |
Art Unit(s) | 2900, 2902, 2912, 2916 |
Total Applications | 11268 |
Issued Applications | 11164 |
Pending Applications | 13 |
Abandoned Applications | 89 |
Applications
Application number | Title of the application | Filing Date | Status |
---|---|---|---|
Array
(
[id] => 18540903
[patent_doc_number] => 20230246014
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-08-03
[patent_title] => SEMICONDUCTOR DEVICE WITH CAPACITOR AND METHOD FOR FORMING THE SAME
[patent_app_type] => utility
[patent_app_number] => 17/587235
[patent_app_country] => US
[patent_app_date] => 2022-01-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5945
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 60
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17587235
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/587235 | Semiconductor device with capacitor and method for forming the same | Jan 27, 2022 | Issued |
Array
(
[id] => 18473167
[patent_doc_number] => 20230207455
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-06-29
[patent_title] => INTEGRATED CIRCUIT STRUCTURE HAVING ANTI-FUSE STRUCTURE
[patent_app_type] => utility
[patent_app_number] => 17/561687
[patent_app_country] => US
[patent_app_date] => 2021-12-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 13635
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -16
[patent_words_short_claim] => 97
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17561687
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/561687 | INTEGRATED CIRCUIT STRUCTURE HAVING ANTI-FUSE STRUCTURE | Dec 22, 2021 | Pending |
Array
(
[id] => 18394949
[patent_doc_number] => 20230163170
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-05-25
[patent_title] => THRESHOLD VOLTAGE TUNING FOR NANORIBBON-BASED TRANSISTORS
[patent_app_type] => utility
[patent_app_number] => 17/530836
[patent_app_country] => US
[patent_app_date] => 2021-11-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 16315
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 88
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17530836
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/530836 | THRESHOLD VOLTAGE TUNING FOR NANORIBBON-BASED TRANSISTORS | Nov 18, 2021 | |
Array
(
[id] => 17566738
[patent_doc_number] => 20220130887
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-04-28
[patent_title] => APPARATUS FOR INTEGRATED MICROWAVE PHOTONICS ON A SAPPHIRE PLATFORM, METHOD OF FORMING SAME, AND APPLICATIONS OF SAME
[patent_app_type] => utility
[patent_app_number] => 17/509635
[patent_app_country] => US
[patent_app_date] => 2021-10-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 27340
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 158
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17509635
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/509635 | APPARATUS FOR INTEGRATED MICROWAVE PHOTONICS ON A SAPPHIRE PLATFORM, METHOD OF FORMING SAME, AND APPLICATIONS OF SAME | Oct 24, 2021 | Pending |
Array
(
[id] => 18148854
[patent_doc_number] => 20230022711
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-01-26
[patent_title] => TUNNELING TRANSISTOR
[patent_app_type] => utility
[patent_app_number] => 17/505815
[patent_app_country] => US
[patent_app_date] => 2021-10-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9290
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 79
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17505815
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/505815 | TUNNELING TRANSISTOR | Oct 19, 2021 | Pending |
Array
(
[id] => 17599599
[patent_doc_number] => 20220149173
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-05-12
[patent_title] => SILICON CARBIDE SEMICONDUCTOR DEVICE, POWER CONVERTER, AND METHOD FOR MANUFACTURING SILICON CARBIDE SEMICONDUCTOR DEVICE
[patent_app_type] => utility
[patent_app_number] => 17/477791
[patent_app_country] => US
[patent_app_date] => 2021-09-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6999
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -9
[patent_words_short_claim] => 101
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17477791
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/477791 | SILICON CARBIDE SEMICONDUCTOR DEVICE, POWER CONVERTER, AND METHOD FOR MANUFACTURING SILICON CARBIDE SEMICONDUCTOR DEVICE | Sep 16, 2021 | Pending |
Array
(
[id] => 17870893
[patent_doc_number] => 20220293630
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-09-15
[patent_title] => SEMICONDUCTOR MEMORY DEVICE
[patent_app_type] => utility
[patent_app_number] => 17/473277
[patent_app_country] => US
[patent_app_date] => 2021-09-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7258
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 225
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17473277
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/473277 | SEMICONDUCTOR MEMORY DEVICE | Sep 12, 2021 | Pending |
Array
(
[id] => 17477373
[patent_doc_number] => 20220084877
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-03-17
[patent_title] => TEMPLATE, METHOD OF MANUFACTURING TEMPLATE, AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
[patent_app_type] => utility
[patent_app_number] => 17/447025
[patent_app_country] => US
[patent_app_date] => 2021-09-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 13015
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -7
[patent_words_short_claim] => 106
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17447025
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/447025 | TEMPLATE, METHOD OF MANUFACTURING TEMPLATE, AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE | Sep 6, 2021 | Pending |
Array
(
[id] => 17615558
[patent_doc_number] => 20220157838
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-05-19
[patent_title] => SEMICONDUCTOR DEVICE AND DATA STORAGE SYSTEM INCLUDING THE SAME
[patent_app_type] => utility
[patent_app_number] => 17/467568
[patent_app_country] => US
[patent_app_date] => 2021-09-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 13892
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 160
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17467568
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/467568 | SEMICONDUCTOR DEVICE AND DATA STORAGE SYSTEM INCLUDING THE SAME | Sep 6, 2021 | Pending |
Array
(
[id] => 17933522
[patent_doc_number] => 20220328648
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-10-13
[patent_title] => Spacer Features For Nanosheet-Based Devices
[patent_app_type] => utility
[patent_app_number] => 17/465259
[patent_app_country] => US
[patent_app_date] => 2021-09-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 12284
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 87
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17465259
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/465259 | Spacer Features For Nanosheet-Based Devices | Sep 1, 2021 | Pending |
Array
(
[id] => 17986143
[patent_doc_number] => 20220352180
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-11-03
[patent_title] => Semiconductor Devices With Threshold Voltage Modulation Layer
[patent_app_type] => utility
[patent_app_number] => 17/464245
[patent_app_country] => US
[patent_app_date] => 2021-09-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 12730
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 110
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17464245
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/464245 | Semiconductor Devices With Threshold Voltage Modulation Layer | Aug 31, 2021 | Pending |
Array
(
[id] => 18229146
[patent_doc_number] => 20230068140
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-03-02
[patent_title] => MULTIGATE DEVICE WITH STRESSOR LAYERS AND METHOD OF FABRICATING THEREOF
[patent_app_type] => utility
[patent_app_number] => 17/446420
[patent_app_country] => US
[patent_app_date] => 2021-08-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 10204
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 106
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17446420
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/446420 | MULTIGATE DEVICE WITH STRESSOR LAYERS AND METHOD OF FABRICATING THEREOF | Aug 29, 2021 | Pending |
Array
(
[id] => 18224444
[patent_doc_number] => 20230063438
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-03-02
[patent_title] => SEMICONDUCTOR STRUCTURE HAVING SELF-ALIGNED CONDUCTIVE STRUCTURE AND METHOD FOR FORMING THE SEMICONDUCTOR STRUCTURE
[patent_app_type] => utility
[patent_app_number] => 17/461155
[patent_app_country] => US
[patent_app_date] => 2021-08-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6744
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 106
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17461155
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/461155 | SEMICONDUCTOR STRUCTURE HAVING SELF-ALIGNED CONDUCTIVE STRUCTURE AND METHOD FOR FORMING THE SEMICONDUCTOR STRUCTURE | Aug 29, 2021 | Pending |
Array
(
[id] => 18228805
[patent_doc_number] => 20230067799
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-03-02
[patent_title] => SEMICONDUCTOR DEVICE HAVING AIR GAP AND METHOD OF FABRICATING THEREOF
[patent_app_type] => utility
[patent_app_number] => 17/446419
[patent_app_country] => US
[patent_app_date] => 2021-08-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9727
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 86
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17446419
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/446419 | SEMICONDUCTOR DEVICE HAVING AIR GAP AND METHOD OF FABRICATING THEREOF | Aug 29, 2021 | Pending |
Array
(
[id] => 17477562
[patent_doc_number] => 20220085066
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-03-17
[patent_title] => METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
[patent_app_type] => utility
[patent_app_number] => 17/459856
[patent_app_country] => US
[patent_app_date] => 2021-08-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4856
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -11
[patent_words_short_claim] => 24
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17459856
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/459856 | METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE | Aug 26, 2021 | Pending |
Array
(
[id] => 17432096
[patent_doc_number] => 20220059806
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-02-24
[patent_title] => ELECTRONIC DEVICE
[patent_app_type] => utility
[patent_app_number] => 17/404485
[patent_app_country] => US
[patent_app_date] => 2021-08-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 21157
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -29
[patent_words_short_claim] => 92
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17404485
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/404485 | ELECTRONIC DEVICE | Aug 16, 2021 | Pending |
Array
(
[id] => 18195310
[patent_doc_number] => 20230048829
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-02-16
[patent_title] => Isolation Structures
[patent_app_type] => utility
[patent_app_number] => 17/402079
[patent_app_country] => US
[patent_app_date] => 2021-08-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 10444
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 123
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17402079
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/402079 | Isolation Structures | Aug 12, 2021 | Pending |
Array
(
[id] => 19138165
[patent_doc_number] => 11973141
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-04-30
[patent_title] => Nanosheet transistor with ferroelectric region
[patent_app_type] => utility
[patent_app_number] => 17/397068
[patent_app_country] => US
[patent_app_date] => 2021-08-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 19
[patent_no_of_words] => 8964
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 87
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17397068
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/397068 | NANOSHEET TRANSISTOR WITH FERROELECTRIC REGION | Aug 8, 2021 | Pending |
Array
(
[id] => 18167183
[patent_doc_number] => 20230033790
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-02-02
[patent_title] => Device Structure With Reduced Leakage Current
[patent_app_type] => utility
[patent_app_number] => 17/389541
[patent_app_country] => US
[patent_app_date] => 2021-07-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 16012
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 137
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17389541
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/389541 | Device Structure With Reduced Leakage Current | Jul 29, 2021 | Pending |
Array
(
[id] => 18456179
[patent_doc_number] => 20230197461
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-06-22
[patent_title] => Method for Manufacturing Semiconductor Structure, and Semiconductor Structure
[patent_app_type] => utility
[patent_app_number] => 17/603320
[patent_app_country] => US
[patent_app_date] => 2021-07-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6405
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -19
[patent_words_short_claim] => 188
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17603320
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/603320 | Method for Manufacturing Semiconductor Structure, and Semiconductor Structure | Jul 19, 2021 | Pending |