Search

Terry A. Wallace

Examiner (ID: 910, Phone: (571)272-2630 , Office: P/2916 )

Most Active Art Unit
2916
Art Unit(s)
2916, 2912, 2900, 2902
Total Applications
11456
Issued Applications
11361
Pending Applications
3
Abandoned Applications
90

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17232262 [patent_doc_number] => 20210358819 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-11-18 [patent_title] => USING A TRAINED NEURAL NETWORK FOR USE IN IN-SITU MONITORING DURING POLISHING AND POLISHING SYSTEM [patent_app_type] => utility [patent_app_number] => 17/317501 [patent_app_country] => US [patent_app_date] => 2021-05-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7786 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17317501 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/317501
Using a trained neural network for use in in-situ monitoring during polishing and polishing system May 10, 2021 Issued
Array ( [id] => 18913136 [patent_doc_number] => 11876125 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-01-16 [patent_title] => Method of making a plurality of high density logic elements with advanced CMOS device layout [patent_app_type] => utility [patent_app_number] => 17/316019 [patent_app_country] => US [patent_app_date] => 2021-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 37 [patent_no_of_words] => 8178 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 215 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17316019 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/316019
Method of making a plurality of high density logic elements with advanced CMOS device layout May 9, 2021 Issued
Array ( [id] => 18935454 [patent_doc_number] => 11887897 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-01-30 [patent_title] => High precision 3D metal stacking for a plurality of 3D devices [patent_app_type] => utility [patent_app_number] => 17/237628 [patent_app_country] => US [patent_app_date] => 2021-04-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 26 [patent_no_of_words] => 9851 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 215 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17237628 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/237628
High precision 3D metal stacking for a plurality of 3D devices Apr 21, 2021 Issued
Array ( [id] => 17583257 [patent_doc_number] => 20220140112 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-05-05 [patent_title] => HIGH DENSITY 3D LAYOUT ENHANCEMENT OF MULTIPLE CMOS DEVICES [patent_app_type] => utility [patent_app_number] => 17/237609 [patent_app_country] => US [patent_app_date] => 2021-04-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8236 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17237609 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/237609
High density 3D layout enhancement of multiple CMOS devices Apr 21, 2021 Issued
Array ( [id] => 17011056 [patent_doc_number] => 20210242217 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-08-05 [patent_title] => Flexible Merge Scheme for Source/Drain Epitaxy Regions [patent_app_type] => utility [patent_app_number] => 17/234201 [patent_app_country] => US [patent_app_date] => 2021-04-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5948 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17234201 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/234201
Flexible merge scheme for source/drain epitaxy regions Apr 18, 2021 Issued
Array ( [id] => 17040618 [patent_doc_number] => 20210257254 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-08-19 [patent_title] => Methods for Forming Contact Plugs with Reduced Corrosion [patent_app_type] => utility [patent_app_number] => 17/234136 [patent_app_country] => US [patent_app_date] => 2021-04-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5275 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17234136 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/234136
Methods for forming contact plugs with reduced corrosion Apr 18, 2021 Issued
Array ( [id] => 18562609 [patent_doc_number] => 11727859 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-08-15 [patent_title] => Display panel and display device [patent_app_type] => utility [patent_app_number] => 17/224463 [patent_app_country] => US [patent_app_date] => 2021-04-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 39 [patent_no_of_words] => 19460 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 346 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17224463 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/224463
Display panel and display device Apr 6, 2021 Issued
Array ( [id] => 17752808 [patent_doc_number] => 20220231013 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-07-21 [patent_title] => STACKED SEMICONDUCTOR DEVICE HAVING MIRROR-SYMMETRIC PATTERN [patent_app_type] => utility [patent_app_number] => 17/223829 [patent_app_country] => US [patent_app_date] => 2021-04-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8711 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17223829 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/223829
Stacked semiconductor device having mirror-symmetric pattern Apr 5, 2021 Issued
Array ( [id] => 17566584 [patent_doc_number] => 20220130733 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-04-28 [patent_title] => SEMICONDUCTOR DEVICE INCLUDING A TEST DUMMY PATTERN, METHOD OF MANUFACTURING THE SEMICONDUCTOR DEVICE AND METHOD OF INSPECTING AN ERROR USING THE TEST DUMMY PATTERN [patent_app_type] => utility [patent_app_number] => 17/208903 [patent_app_country] => US [patent_app_date] => 2021-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4830 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -9 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17208903 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/208903
SEMICONDUCTOR DEVICE INCLUDING A TEST DUMMY PATTERN, METHOD OF MANUFACTURING THE SEMICONDUCTOR DEVICE AND METHOD OF INSPECTING AN ERROR USING THE TEST DUMMY PATTERN Mar 21, 2021 Abandoned
Array ( [id] => 19539400 [patent_doc_number] => 12131957 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-10-29 [patent_title] => Manufacturing process with atomic level inspection [patent_app_type] => utility [patent_app_number] => 17/199879 [patent_app_country] => US [patent_app_date] => 2021-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 17 [patent_no_of_words] => 6885 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17199879 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/199879
Manufacturing process with atomic level inspection Mar 11, 2021 Issued
Array ( [id] => 16920717 [patent_doc_number] => 20210193809 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-06-24 [patent_title] => Laterally Diffused Metal Oxide Semiconductor with Gate Poly Contact within Source Window [patent_app_type] => utility [patent_app_number] => 17/197188 [patent_app_country] => US [patent_app_date] => 2021-03-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4424 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => 0 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17197188 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/197188
Laterally diffused metal oxide semiconductor with gate poly contact within source window Mar 9, 2021 Issued
Array ( [id] => 17085576 [patent_doc_number] => 20210280583 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-09-09 [patent_title] => SEMICONDUCTOR STRUCTURE AND FORMATION METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/249542 [patent_app_country] => US [patent_app_date] => 2021-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9648 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17249542 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/249542
SEMICONDUCTOR STRUCTURE AND FORMATION METHOD THEREOF Mar 3, 2021 Abandoned
Array ( [id] => 19244628 [patent_doc_number] => 12015083 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-06-18 [patent_title] => Thin-sheet FinFET device [patent_app_type] => utility [patent_app_number] => 17/189039 [patent_app_country] => US [patent_app_date] => 2021-03-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 42 [patent_figures_cnt] => 69 [patent_no_of_words] => 13859 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17189039 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/189039
Thin-sheet FinFET device Feb 28, 2021 Issued
Array ( [id] => 16905036 [patent_doc_number] => 20210183952 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-06-17 [patent_title] => DISPLAY SUBSTRATE, LIGHT FIELD DISPLAY APPARATUS AND METHOD FOR DRIVING THE SAME [patent_app_type] => utility [patent_app_number] => 17/184017 [patent_app_country] => US [patent_app_date] => 2021-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6013 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17184017 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/184017
Display substrate, light field display apparatus and method for driving the same Feb 23, 2021 Issued
Array ( [id] => 17787851 [patent_doc_number] => 11410987 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-08-09 [patent_title] => Chip and method for manufacturing a chip [patent_app_type] => utility [patent_app_number] => 17/176196 [patent_app_country] => US [patent_app_date] => 2021-02-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 5585 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 232 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17176196 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/176196
Chip and method for manufacturing a chip Feb 15, 2021 Issued
Array ( [id] => 16827909 [patent_doc_number] => 20210143202 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-05-13 [patent_title] => IMAGE SENSORS WITH LIGHT CHANNELING REFLECTIVE LAYERS THEREIN [patent_app_type] => utility [patent_app_number] => 17/157205 [patent_app_country] => US [patent_app_date] => 2021-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5744 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => 0 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17157205 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/157205
Image sensors with light channeling reflective layers therein Jan 24, 2021 Issued
Array ( [id] => 16920824 [patent_doc_number] => 20210193916 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-06-24 [patent_title] => PHASE CHANGE MEMORY CELL WITH CONSTRICTION STRUCTURE [patent_app_type] => utility [patent_app_number] => 17/135102 [patent_app_country] => US [patent_app_date] => 2020-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13499 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => 0 [patent_words_short_claim] => 253 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17135102 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/135102
PHASE CHANGE MEMORY CELL WITH CONSTRICTION STRUCTURE Dec 27, 2020 Abandoned
Array ( [id] => 16920566 [patent_doc_number] => 20210193658 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-06-24 [patent_title] => INTEGRATED DEVICE WITH DEEP PLUG UNDER SHALLOW TRENCH [patent_app_type] => utility [patent_app_number] => 17/124671 [patent_app_country] => US [patent_app_date] => 2020-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6962 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17124671 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/124671
INTEGRATED DEVICE WITH DEEP PLUG UNDER SHALLOW TRENCH Dec 16, 2020 Abandoned
Array ( [id] => 16811948 [patent_doc_number] => 20210134503 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-05-06 [patent_title] => SPIN-ORBIT-TORQUE MAGNETIZATION ROTATIONAL ELEMENT, SPIN-ORBIT-TORQUE MAGNETORESISTANCE EFFECT ELEMENT, AND SPIN-ORBIT-TORQUE MAGNETIZATION ROTATIONAL ELEMENT MANUFACTURING METHOD [patent_app_type] => utility [patent_app_number] => 17/123514 [patent_app_country] => US [patent_app_date] => 2020-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8376 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17123514 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/123514
Spin-orbit-torque magnetization rotational element, spin-orbit-torque magnetoresistance effect element, and spin-orbit-torque magnetization rotational element manufacturing method Dec 15, 2020 Issued
Array ( [id] => 18983717 [patent_doc_number] => 11908907 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-02-20 [patent_title] => VFET contact formation [patent_app_type] => utility [patent_app_number] => 17/118853 [patent_app_country] => US [patent_app_date] => 2020-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 14 [patent_no_of_words] => 6108 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17118853 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/118853
VFET contact formation Dec 10, 2020 Issued
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