
Terry A. Wallace
Examiner (ID: 910, Phone: (571)272-2630 , Office: P/2916 )
| Most Active Art Unit | 2916 |
| Art Unit(s) | 2916, 2912, 2900, 2902 |
| Total Applications | 11456 |
| Issued Applications | 11361 |
| Pending Applications | 3 |
| Abandoned Applications | 90 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 18190625
[patent_doc_number] => 11581226
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-02-14
[patent_title] => Semiconductor device with tunable epitaxy structures and method of forming the same
[patent_app_type] => utility
[patent_app_number] => 16/938340
[patent_app_country] => US
[patent_app_date] => 2020-07-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 30
[patent_figures_cnt] => 79
[patent_no_of_words] => 9848
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 305
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16938340
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/938340 | Semiconductor device with tunable epitaxy structures and method of forming the same | Jul 23, 2020 | Issued |
Array
(
[id] => 18983742
[patent_doc_number] => 11908932
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-02-20
[patent_title] => Apparatuses comprising vertical transistors having gate electrodes at least partially recessed within channel regions, and related methods and systems
[patent_app_type] => utility
[patent_app_number] => 16/936983
[patent_app_country] => US
[patent_app_date] => 2020-07-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 19
[patent_no_of_words] => 13472
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 167
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16936983
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/936983 | Apparatuses comprising vertical transistors having gate electrodes at least partially recessed within channel regions, and related methods and systems | Jul 22, 2020 | Issued |
Array
(
[id] => 17070738
[patent_doc_number] => 20210272955
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-09-02
[patent_title] => METHOD OF MANUFACTURING SEMICONDUCTOR DEVICES AND SEMICONDUCTOR DEVICES
[patent_app_type] => utility
[patent_app_number] => 16/934916
[patent_app_country] => US
[patent_app_date] => 2020-07-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 14680
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 116
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16934916
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/934916 | Method of manufacturing semiconductor devices and semiconductor devices | Jul 20, 2020 | Issued |
Array
(
[id] => 16425211
[patent_doc_number] => 20200350409
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-11-05
[patent_title] => Growth of Single Atom Chains for Nano-Electronics and Quantum Circuits
[patent_app_type] => utility
[patent_app_number] => 16/931246
[patent_app_country] => US
[patent_app_date] => 2020-07-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 2435
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -16
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16931246
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/931246 | Growth of Single Atom Chains for Nano-Electronics and Quantum Circuits | Jul 15, 2020 | Abandoned |
Array
(
[id] => 17359854
[patent_doc_number] => 20220020650
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-01-20
[patent_title] => DEFECTIVE CHIP PROCESSING METHOD
[patent_app_type] => utility
[patent_app_number] => 16/930136
[patent_app_country] => US
[patent_app_date] => 2020-07-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 2652
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -14
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16930136
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/930136 | DEFECTIVE CHIP PROCESSING METHOD | Jul 14, 2020 | Abandoned |
Array
(
[id] => 18131285
[patent_doc_number] => 11557502
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-01-17
[patent_title] => Method for forming trenches
[patent_app_type] => utility
[patent_app_number] => 16/925857
[patent_app_country] => US
[patent_app_date] => 2020-07-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 32
[patent_no_of_words] => 8704
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 321
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16925857
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/925857 | Method for forming trenches | Jul 9, 2020 | Issued |
Array
(
[id] => 17010931
[patent_doc_number] => 20210242092
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-08-05
[patent_title] => Novel Structures for Tuning Threshold Voltage
[patent_app_type] => utility
[patent_app_number] => 16/925893
[patent_app_country] => US
[patent_app_date] => 2020-07-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 11974
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 41
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16925893
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/925893 | Structures for tuning threshold voltage | Jul 9, 2020 | Issued |
Array
(
[id] => 16578710
[patent_doc_number] => 20210013111
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-01-14
[patent_title] => METHOD FOR THRESHOLD VOLTAGE TUNING THROUGH SELECTIVE DEPOSITION OF HIGH-K METAL GATE (HKMG) FILM STACKS
[patent_app_type] => utility
[patent_app_number] => 16/924937
[patent_app_country] => US
[patent_app_date] => 2020-07-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 11227
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 200
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16924937
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/924937 | Method for threshold voltage tuning through selective deposition of high-K metal gate (HKMG) film stacks | Jul 8, 2020 | Issued |
Array
(
[id] => 17978592
[patent_doc_number] => 11495464
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-11-08
[patent_title] => Semiconductor device and method
[patent_app_type] => utility
[patent_app_number] => 16/923658
[patent_app_country] => US
[patent_app_date] => 2020-07-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 28
[patent_figures_cnt] => 66
[patent_no_of_words] => 11230
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 115
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16923658
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/923658 | Semiconductor device and method | Jul 7, 2020 | Issued |
Array
(
[id] => 17295500
[patent_doc_number] => 20210391339
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-12-16
[patent_title] => STATIC RANDOM ACCESS MEMORY AND METHOD FOR FABRICATING THE SAME
[patent_app_type] => utility
[patent_app_number] => 16/923117
[patent_app_country] => US
[patent_app_date] => 2020-07-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4268
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -16
[patent_words_short_claim] => 90
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16923117
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/923117 | Static random access memory and method for fabricating the same | Jul 7, 2020 | Issued |
Array
(
[id] => 17353143
[patent_doc_number] => 11227788
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-01-18
[patent_title] => Method of forming isolation layer
[patent_app_type] => utility
[patent_app_number] => 16/921015
[patent_app_country] => US
[patent_app_date] => 2020-07-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 30
[patent_figures_cnt] => 30
[patent_no_of_words] => 5733
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 164
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16921015
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/921015 | Method of forming isolation layer | Jul 5, 2020 | Issued |
Array
(
[id] => 16846012
[patent_doc_number] => 11018108
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-05-25
[patent_title] => Method of fabricating semiconductor package
[patent_app_type] => utility
[patent_app_number] => 16/914384
[patent_app_country] => US
[patent_app_date] => 2020-06-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 25
[patent_no_of_words] => 9729
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 240
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16914384
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/914384 | Method of fabricating semiconductor package | Jun 27, 2020 | Issued |
Array
(
[id] => 16920565
[patent_doc_number] => 20210193657
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-06-24
[patent_title] => SEMICONDUCTOR DEVICE
[patent_app_type] => utility
[patent_app_number] => 16/910385
[patent_app_country] => US
[patent_app_date] => 2020-06-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7465
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 179
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16910385
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/910385 | Semiconductor device | Jun 23, 2020 | Issued |
Array
(
[id] => 18120776
[patent_doc_number] => 11552175
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-01-10
[patent_title] => Semiconductor device
[patent_app_type] => utility
[patent_app_number] => 16/908799
[patent_app_country] => US
[patent_app_date] => 2020-06-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 16
[patent_no_of_words] => 9016
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 337
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16908799
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/908799 | Semiconductor device | Jun 22, 2020 | Issued |
Array
(
[id] => 17780299
[patent_doc_number] => 20220246649
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-08-04
[patent_title] => ARRAY SUBSTRATE AND OLED DISPLAY PANEL
[patent_app_type] => utility
[patent_app_number] => 16/980095
[patent_app_country] => US
[patent_app_date] => 2020-06-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6634
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 171
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16980095
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/980095 | Array substrate and OLED display panel | Jun 21, 2020 | Issued |
Array
(
[id] => 16692290
[patent_doc_number] => 20210074769
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-03-11
[patent_title] => DISPLAY DEVICE
[patent_app_type] => utility
[patent_app_number] => 16/904715
[patent_app_country] => US
[patent_app_date] => 2020-06-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 33173
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -25
[patent_words_short_claim] => 143
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16904715
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/904715 | Display device | Jun 17, 2020 | Issued |
Array
(
[id] => 17303023
[patent_doc_number] => 20210398862
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-12-23
[patent_title] => STRUCTURE WITH DIFFERENT STRESS-INDUCING ISOLATION DIELECTRICS FOR DIFFERENT POLARITY FETS
[patent_app_type] => utility
[patent_app_number] => 16/903559
[patent_app_country] => US
[patent_app_date] => 2020-06-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6190
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 56
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16903559
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/903559 | Structure with different stress-inducing isolation dielectrics for different polarity FETs | Jun 16, 2020 | Issued |
Array
(
[id] => 18331757
[patent_doc_number] => 11637010
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-04-25
[patent_title] => System and method of forming a porous low-k structure
[patent_app_type] => utility
[patent_app_number] => 16/895800
[patent_app_country] => US
[patent_app_date] => 2020-06-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 16
[patent_no_of_words] => 5419
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 110
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16895800
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/895800 | System and method of forming a porous low-k structure | Jun 7, 2020 | Issued |
Array
(
[id] => 16301352
[patent_doc_number] => 20200287075
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-09-10
[patent_title] => LIGHT-EMITTING DEVICE
[patent_app_type] => utility
[patent_app_number] => 16/883742
[patent_app_country] => US
[patent_app_date] => 2020-05-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6591
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -14
[patent_words_short_claim] => 148
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16883742
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/883742 | Light-emitting device | May 25, 2020 | Issued |
Array
(
[id] => 16707832
[patent_doc_number] => 10957776
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-03-23
[patent_title] => Method of fabricating MOSFET
[patent_app_type] => utility
[patent_app_number] => 16/880019
[patent_app_country] => US
[patent_app_date] => 2020-05-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 35
[patent_no_of_words] => 10403
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 311
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16880019
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/880019 | Method of fabricating MOSFET | May 20, 2020 | Issued |