Terry D. Cunningham

Array ( [id] => 4182343 [patent_doc_number] => 06084446 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-07-04 [patent_title] => 'Power on reset circuit' [patent_app_type] => 1 [patent_app_number] => 9/101679 [patent_app_country] => US [patent_app_date] => 1998-06-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 3840 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 341 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/084/06084446.pdf [firstpage_image] =>[orig_patent_app_number] => 101679 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4256134 [patent_doc_number] => 06137346 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-24 [patent_title] => 'Temperature tracking voltage to current converter' [patent_app_type] => 1 [patent_app_number] => 9/067314 [patent_app_country] => US [patent_app_date] => 1998-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 4669 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/137/06137346.pdf [firstpage_image] =>[orig_patent_app_number] => 067314 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3991204 [patent_doc_number] => 05910739 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-06-08 [patent_title] => 'Power-up/interrupt delay timer' [patent_app_type] => 1 [patent_app_number] => 9/065390 [patent_app_country] => US [patent_app_date] => 1998-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 2765 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/910/05910739.pdf [firstpage_image] =>[orig_patent_app_number] => 065390 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4415943 [patent_doc_number] => 06265907 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-24 [patent_title] => 'Signal transmission circuit having intermediate amplifier circuit' [patent_app_type] => 1 [patent_app_number] => 9/053365 [patent_app_country] => US [patent_app_date] => 1998-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 17 [patent_no_of_words] => 6018 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 299 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/265/06265907.pdf [firstpage_image] =>[orig_patent_app_number] => 053365 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3982369 [patent_doc_number] => 05917338 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-06-29 [patent_title] => 'Area-efficient implication circuits for very dense Lukasiewicz logic arrays' [patent_app_type] => 1 [patent_app_number] => 9/047753 [patent_app_country] => US [patent_app_date] => 1998-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 43 [patent_no_of_words] => 5504 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/917/05917338.pdf [firstpage_image] =>[orig_patent_app_number] => 047753 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3920263 [patent_doc_number] => 06002293 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-12-14 [patent_title] => 'High transconductance voltage reference cell' [patent_app_type] => 1 [patent_app_number] => 9/047123 [patent_app_country] => US [patent_app_date] => 1998-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5243 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 283 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/002/06002293.pdf [firstpage_image] =>[orig_patent_app_number] => 047123 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4104351 [patent_doc_number] => 06097242 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-01 [patent_title] => 'Threshold voltage compensation circuits for low voltage and low power CMOS integrated circuits' [patent_app_type] => 1 [patent_app_number] => 9/031976 [patent_app_country] => US [patent_app_date] => 1998-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 11 [patent_no_of_words] => 2836 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/097/06097242.pdf [firstpage_image] =>[orig_patent_app_number] => 031976 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4134934 [patent_doc_number] => 06127879 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-03 [patent_title] => 'Multi-channel overvoltage protection circuit' [patent_app_type] => 1 [patent_app_number] => 9/030902 [patent_app_country] => US [patent_app_date] => 1998-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1355 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/127/06127879.pdf [firstpage_image] =>[orig_patent_app_number] => 030902 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3934336 [patent_doc_number] => 05952871 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-14 [patent_title] => 'Substrate voltage generating circuit of semiconductor memory device' [patent_app_type] => 1 [patent_app_number] => 9/031092 [patent_app_country] => US [patent_app_date] => 1998-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 5510 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 441 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/952/05952871.pdf [firstpage_image] =>[orig_patent_app_number] => 031092 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4192025 [patent_doc_number] => 06150874 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-21 [patent_title] => 'Circuit layout and process for generating a supply DC voltage' [patent_app_type] => 1 [patent_app_number] => 9/030371 [patent_app_country] => US [patent_app_date] => 1998-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 3791 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 269 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/150/06150874.pdf [firstpage_image] =>[orig_patent_app_number] => 030371 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4246560 [patent_doc_number] => 06091283 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-07-18 [patent_title] => 'Sub-threshold leakage tuning circuit' [patent_app_type] => 1 [patent_app_number] => 9/028469 [patent_app_country] => US [patent_app_date] => 1998-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 2293 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/091/06091283.pdf [firstpage_image] =>[orig_patent_app_number] => 028469 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4148103 [patent_doc_number] => 06060946 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-09 [patent_title] => 'Semiconductor device having improved immunity to power supply voltage fluctuations' [patent_app_type] => 1 [patent_app_number] => 9/025662 [patent_app_country] => US [patent_app_date] => 1998-02-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 15 [patent_no_of_words] => 5107 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/060/06060946.pdf [firstpage_image] =>[orig_patent_app_number] => 025662 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4229678 [patent_doc_number] => 06011429 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-01-04 [patent_title] => 'Reference voltage generating device' [patent_app_type] => 1 [patent_app_number] => 9/016456 [patent_app_country] => US [patent_app_date] => 1998-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 3585 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/011/06011429.pdf [firstpage_image] =>[orig_patent_app_number] => 016456 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4165492 [patent_doc_number] => 06114893 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-05 [patent_title] => 'Gain stage with improved power supply rejection' [patent_app_type] => 1 [patent_app_number] => 9/015485 [patent_app_country] => US [patent_app_date] => 1998-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 4 [patent_no_of_words] => 1007 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/114/06114893.pdf [firstpage_image] =>[orig_patent_app_number] => 015485 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3955872 [patent_doc_number] => 05999034 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-12-07 [patent_title] => 'Pull-down driver circuit for 3.3V I/O buffer using 1.9V fabrication process' [patent_app_type] => 1 [patent_app_number] => 9/014530 [patent_app_country] => US [patent_app_date] => 1998-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 1986 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 197 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/999/05999034.pdf [firstpage_image] =>[orig_patent_app_number] => 014530 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 935814 [patent_doc_number] => 06975164 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-12-13 [patent_title] => 'Method and device for generating constant voltage' [patent_app_type] => utility [patent_app_number] => 09/014401 [patent_app_country] => US [patent_app_date] => 1998-01-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 18 [patent_no_of_words] => 9364 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/975/06975164.pdf [firstpage_image] =>[orig_patent_app_number] => 09014401 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4149890 [patent_doc_number] => 06031405 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-29 [patent_title] => 'ESD protection circuit immune to latch-up during normal operation' [patent_app_type] => 1 [patent_app_number] => 9/014186 [patent_app_country] => US [patent_app_date] => 1998-01-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 3307 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/031/06031405.pdf [firstpage_image] =>[orig_patent_app_number] => 014186 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4412334 [patent_doc_number] => 06271706 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-07 [patent_title] => 'Divided voltage de-coupling structure' [patent_app_type] => 1 [patent_app_number] => 9/010631 [patent_app_country] => US [patent_app_date] => 1998-01-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 1638 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/271/06271706.pdf [firstpage_image] =>[orig_patent_app_number] => 010631 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4125677 [patent_doc_number] => 06072358 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-06-06 [patent_title] => 'High voltage pump circuit with reduced oxide stress' [patent_app_type] => 1 [patent_app_number] => 9/008619 [patent_app_country] => US [patent_app_date] => 1998-01-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 2892 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/072/06072358.pdf [firstpage_image] =>[orig_patent_app_number] => 008619 [rel_patent_id] =>[rel_patent_doc_number] =>)