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Terry D. Cunningham

Examiner (ID: 11164)

Most Active Art Unit
2816
Art Unit(s)
2504, 2816
Total Applications
1191
Issued Applications
935
Pending Applications
36
Abandoned Applications
220

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3906007 [patent_doc_number] => 05751185 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-05-12 [patent_title] => 'Low pass filter circuit utilizing transistors as inductive elements' [patent_app_type] => 1 [patent_app_number] => 8/827780 [patent_app_country] => US [patent_app_date] => 1997-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 45 [patent_figures_cnt] => 65 [patent_no_of_words] => 20582 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/751/05751185.pdf [firstpage_image] =>[orig_patent_app_number] => 827780 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/827780
Low pass filter circuit utilizing transistors as inductive elements Apr 10, 1997 Issued
Array ( [id] => 4115447 [patent_doc_number] => 06057725 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-02 [patent_title] => 'Protection circuit for use during burn-in testing' [patent_app_type] => 1 [patent_app_number] => 8/841990 [patent_app_country] => US [patent_app_date] => 1997-04-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 9682 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/057/06057725.pdf [firstpage_image] =>[orig_patent_app_number] => 841990 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/841990
Protection circuit for use during burn-in testing Apr 7, 1997 Issued
Array ( [id] => 1028794 [patent_doc_number] => 06882215 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-04-19 [patent_title] => 'Substrate bias generator in semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 08/825582 [patent_app_country] => US [patent_app_date] => 1997-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 4488 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 220 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/882/06882215.pdf [firstpage_image] =>[orig_patent_app_number] => 08825582 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/825582
Substrate bias generator in semiconductor memory device Mar 30, 1997 Issued
Array ( [id] => 4004839 [patent_doc_number] => 05923206 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-07-13 [patent_title] => 'Charge injection cancellation technique' [patent_app_type] => 1 [patent_app_number] => 8/827284 [patent_app_country] => US [patent_app_date] => 1997-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 2405 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/923/05923206.pdf [firstpage_image] =>[orig_patent_app_number] => 827284 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/827284
Charge injection cancellation technique Mar 26, 1997 Issued
Array ( [id] => 4160799 [patent_doc_number] => 06124744 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-26 [patent_title] => 'Electronic circuit apparatus having circuits for effectively compensating for clock skew' [patent_app_type] => 1 [patent_app_number] => 8/824743 [patent_app_country] => US [patent_app_date] => 1997-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 28 [patent_no_of_words] => 7264 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/124/06124744.pdf [firstpage_image] =>[orig_patent_app_number] => 824743 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/824743
Electronic circuit apparatus having circuits for effectively compensating for clock skew Mar 25, 1997 Issued
Array ( [id] => 3854117 [patent_doc_number] => 05719522 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-02-17 [patent_title] => 'Reference voltage generating circuit having reduced current consumption with varying loads' [patent_app_type] => 1 [patent_app_number] => 8/814935 [patent_app_country] => US [patent_app_date] => 1997-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 2873 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/719/05719522.pdf [firstpage_image] =>[orig_patent_app_number] => 814935 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/814935
Reference voltage generating circuit having reduced current consumption with varying loads Mar 11, 1997 Issued
Array ( [id] => 4413518 [patent_doc_number] => 06172547 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-09 [patent_title] => 'Semiconductor integrated circuit capable of driving large loads within its internal core area' [patent_app_type] => 1 [patent_app_number] => 8/811275 [patent_app_country] => US [patent_app_date] => 1997-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 3081 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 241 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/172/06172547.pdf [firstpage_image] =>[orig_patent_app_number] => 811275 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/811275
Semiconductor integrated circuit capable of driving large loads within its internal core area Mar 3, 1997 Issued
Array ( [id] => 4241166 [patent_doc_number] => 06075407 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-06-13 [patent_title] => 'Low power digital CMOS compatible bandgap reference' [patent_app_type] => 1 [patent_app_number] => 8/808187 [patent_app_country] => US [patent_app_date] => 1997-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 3475 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/075/06075407.pdf [firstpage_image] =>[orig_patent_app_number] => 808187 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/808187
Low power digital CMOS compatible bandgap reference Feb 27, 1997 Issued
Array ( [id] => 3931670 [patent_doc_number] => 05945871 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-31 [patent_title] => 'Process for temperature stabilization' [patent_app_type] => 1 [patent_app_number] => 8/765282 [patent_app_country] => US [patent_app_date] => 1997-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2689 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/945/05945871.pdf [firstpage_image] =>[orig_patent_app_number] => 765282 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/765282
Process for temperature stabilization Feb 25, 1997 Issued
Array ( [id] => 3777962 [patent_doc_number] => 05774010 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-30 [patent_title] => 'MOS four-quadrant multiplier including the voltage-controlled-three-transistor V-I converters' [patent_app_type] => 1 [patent_app_number] => 8/798637 [patent_app_country] => US [patent_app_date] => 1997-02-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 17 [patent_no_of_words] => 8990 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 293 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/774/05774010.pdf [firstpage_image] =>[orig_patent_app_number] => 798637 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/798637
MOS four-quadrant multiplier including the voltage-controlled-three-transistor V-I converters Feb 10, 1997 Issued
Array ( [id] => 3982834 [patent_doc_number] => 05917367 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-06-29 [patent_title] => 'Power supply solution for mixed signal circuits' [patent_app_type] => 1 [patent_app_number] => 8/798991 [patent_app_country] => US [patent_app_date] => 1997-02-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 4791 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/917/05917367.pdf [firstpage_image] =>[orig_patent_app_number] => 798991 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/798991
Power supply solution for mixed signal circuits Feb 10, 1997 Issued
Array ( [id] => 3703448 [patent_doc_number] => 05677643 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-10-14 [patent_title] => 'Potential detecting circuit which suppresses the adverse effects and eliminates dependency of detected potential on power supply potential' [patent_app_type] => 1 [patent_app_number] => 8/798996 [patent_app_country] => US [patent_app_date] => 1997-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 19 [patent_no_of_words] => 5713 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 20 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/677/05677643.pdf [firstpage_image] =>[orig_patent_app_number] => 798996 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/798996
Potential detecting circuit which suppresses the adverse effects and eliminates dependency of detected potential on power supply potential Feb 6, 1997 Issued
Array ( [id] => 4225693 [patent_doc_number] => 06087895 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-07-11 [patent_title] => 'Semiconductor integrated circuit having power lines separately routed to input circuits and circuit unit using it' [patent_app_type] => 1 [patent_app_number] => 8/790930 [patent_app_country] => US [patent_app_date] => 1997-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 8467 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/087/06087895.pdf [firstpage_image] =>[orig_patent_app_number] => 790930 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/790930
Semiconductor integrated circuit having power lines separately routed to input circuits and circuit unit using it Jan 28, 1997 Issued
Array ( [id] => 3943313 [patent_doc_number] => 05929693 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-07-27 [patent_title] => 'Substrate bias generator for semiconductor integrated circuit device' [patent_app_type] => 1 [patent_app_number] => 8/790338 [patent_app_country] => US [patent_app_date] => 1997-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 33 [patent_no_of_words] => 10418 [patent_no_of_claims] => 42 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 199 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/929/05929693.pdf [firstpage_image] =>[orig_patent_app_number] => 790338 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/790338
Substrate bias generator for semiconductor integrated circuit device Jan 27, 1997 Issued
Array ( [id] => 4063490 [patent_doc_number] => 05864251 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-01-26 [patent_title] => 'Method and apparatus for self-resetting logic circuitry' [patent_app_type] => 1 [patent_app_number] => 8/791002 [patent_app_country] => US [patent_app_date] => 1997-01-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 11690 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/864/05864251.pdf [firstpage_image] =>[orig_patent_app_number] => 791002 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/791002
Method and apparatus for self-resetting logic circuitry Jan 26, 1997 Issued
Array ( [id] => 3831862 [patent_doc_number] => 05731731 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-03-24 [patent_title] => 'High efficiency switching regulator with adaptive drive output circuit' [patent_app_type] => 1 [patent_app_number] => 8/786500 [patent_app_country] => US [patent_app_date] => 1997-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6151 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 43 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/731/05731731.pdf [firstpage_image] =>[orig_patent_app_number] => 786500 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/786500
High efficiency switching regulator with adaptive drive output circuit Jan 20, 1997 Issued
Array ( [id] => 3822618 [patent_doc_number] => 05770966 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-23 [patent_title] => 'Area-efficient implication circuits for very dense lukasiewicz logic arrays' [patent_app_type] => 1 [patent_app_number] => 8/783196 [patent_app_country] => US [patent_app_date] => 1997-01-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 43 [patent_no_of_words] => 5503 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 213 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/770/05770966.pdf [firstpage_image] =>[orig_patent_app_number] => 783196 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/783196
Area-efficient implication circuits for very dense lukasiewicz logic arrays Jan 14, 1997 Issued
Array ( [id] => 4104293 [patent_doc_number] => 06097238 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-01 [patent_title] => 'Circuit with ramp-up control and overcoming a threshold voltage loss in an NMOS transistor' [patent_app_type] => 1 [patent_app_number] => 8/782198 [patent_app_country] => US [patent_app_date] => 1997-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 4207 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 328 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/097/06097238.pdf [firstpage_image] =>[orig_patent_app_number] => 782198 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/782198
Circuit with ramp-up control and overcoming a threshold voltage loss in an NMOS transistor Jan 9, 1997 Issued
08/780842 SEMICONDUCTOR DEVICE Jan 8, 1997 Abandoned
Array ( [id] => 3708648 [patent_doc_number] => 05675265 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-10-07 [patent_title] => 'Method of measuring delay time in semiconductor device' [patent_app_type] => 1 [patent_app_number] => 8/781921 [patent_app_country] => US [patent_app_date] => 1996-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3674 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/675/05675265.pdf [firstpage_image] =>[orig_patent_app_number] => 781921 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/781921
Method of measuring delay time in semiconductor device Dec 29, 1996 Issued
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