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Terry D. Cunningham

Examiner (ID: 1940)

Most Active Art Unit
2816
Art Unit(s)
2816, 2504
Total Applications
1191
Issued Applications
935
Pending Applications
36
Abandoned Applications
220

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 2760131 [patent_doc_number] => 05043605 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-08-27 [patent_title] => 'CMOS to ECL output buffer' [patent_app_type] => 1 [patent_app_number] => 7/371356 [patent_app_country] => US [patent_app_date] => 1989-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 2348 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/043/05043605.pdf [firstpage_image] =>[orig_patent_app_number] => 371356 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/371356
CMOS to ECL output buffer Jun 25, 1989 Issued
Array ( [id] => 2737323 [patent_doc_number] => 05039881 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-08-13 [patent_title] => 'High speed, low power input buffer' [patent_app_type] => 1 [patent_app_number] => 7/370657 [patent_app_country] => US [patent_app_date] => 1989-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 1231 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/039/05039881.pdf [firstpage_image] =>[orig_patent_app_number] => 370657 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/370657
High speed, low power input buffer Jun 22, 1989 Issued
Array ( [id] => 2699980 [patent_doc_number] => 04996494 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-02-26 [patent_title] => 'Droop compensated PFN driven transformer for generating high voltage, high energy pulses' [patent_app_type] => 1 [patent_app_number] => 7/366944 [patent_app_country] => US [patent_app_date] => 1989-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 4754 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 618 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/996/04996494.pdf [firstpage_image] =>[orig_patent_app_number] => 366944 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/366944
Droop compensated PFN driven transformer for generating high voltage, high energy pulses Jun 14, 1989 Issued
Array ( [id] => 2770325 [patent_doc_number] => 05006736 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-04-09 [patent_title] => 'Control circuit for rapid gate discharge' [patent_app_type] => 1 [patent_app_number] => 7/365403 [patent_app_country] => US [patent_app_date] => 1989-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 1832 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 365 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/006/05006736.pdf [firstpage_image] =>[orig_patent_app_number] => 365403 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/365403
Control circuit for rapid gate discharge Jun 12, 1989 Issued
Array ( [id] => 2803761 [patent_doc_number] => 05140202 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-08-18 [patent_title] => 'Delay circuit which maintains its delay in a given relationship to a reference time interval' [patent_app_type] => 1 [patent_app_number] => 7/362114 [patent_app_country] => US [patent_app_date] => 1989-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 2548 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/140/05140202.pdf [firstpage_image] =>[orig_patent_app_number] => 362114 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/362114
Delay circuit which maintains its delay in a given relationship to a reference time interval Jun 4, 1989 Issued
Array ( [id] => 2597947 [patent_doc_number] => 04940910 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-07-10 [patent_title] => 'Temperature compensated monolithic delay circuit' [patent_app_type] => 1 [patent_app_number] => 7/360511 [patent_app_country] => US [patent_app_date] => 1989-06-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 5 [patent_no_of_words] => 3784 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/940/04940910.pdf [firstpage_image] =>[orig_patent_app_number] => 360511 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/360511
Temperature compensated monolithic delay circuit Jun 1, 1989 Issued
Array ( [id] => 2674379 [patent_doc_number] => 05034624 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-07-23 [patent_title] => 'Apparatus and method for assuring stable clock generator during oscillator start-up' [patent_app_type] => 1 [patent_app_number] => 7/359185 [patent_app_country] => US [patent_app_date] => 1989-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 7402 [patent_no_of_claims] => 48 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/034/05034624.pdf [firstpage_image] =>[orig_patent_app_number] => 359185 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/359185
Apparatus and method for assuring stable clock generator during oscillator start-up May 30, 1989 Issued
Array ( [id] => 2803707 [patent_doc_number] => 05140199 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1992-08-18 [patent_title] => 'Sense amplifier driver for memory device having reduced power dissipation' [patent_app_type] => 1 [patent_app_number] => 7/358679 [patent_app_country] => US [patent_app_date] => 1989-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 4318 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 300 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/140/05140199.pdf [firstpage_image] =>[orig_patent_app_number] => 358679 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/358679
Sense amplifier driver for memory device having reduced power dissipation May 29, 1989 Issued
Array ( [id] => 2675704 [patent_doc_number] => 05073727 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-12-17 [patent_title] => 'CMOS inverter with noise reduction feedback means' [patent_app_type] => 1 [patent_app_number] => 7/356920 [patent_app_country] => US [patent_app_date] => 1989-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 2851 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/073/05073727.pdf [firstpage_image] =>[orig_patent_app_number] => 356920 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/356920
CMOS inverter with noise reduction feedback means May 24, 1989 Issued
Array ( [id] => 2636212 [patent_doc_number] => 04958093 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-09-18 [patent_title] => 'Voltage clamping circuits with high current capability' [patent_app_type] => 1 [patent_app_number] => 7/356917 [patent_app_country] => US [patent_app_date] => 1989-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 4594 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/958/04958093.pdf [firstpage_image] =>[orig_patent_app_number] => 356917 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/356917
Voltage clamping circuits with high current capability May 24, 1989 Issued
Array ( [id] => 2662041 [patent_doc_number] => 04962344 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-10-09 [patent_title] => 'Segmented waveform generator' [patent_app_type] => 1 [patent_app_number] => 7/356794 [patent_app_country] => US [patent_app_date] => 1989-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 11 [patent_no_of_words] => 3061 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/962/04962344.pdf [firstpage_image] =>[orig_patent_app_number] => 356794 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/356794
Segmented waveform generator May 22, 1989 Issued
07/355939 HIGH-SPEED LOW-POWER SUPPLY-INDEPENDENT TTL COMPATIBLE INPUT BUFFER May 22, 1989 Abandoned
Array ( [id] => 2770253 [patent_doc_number] => 05006732 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-04-09 [patent_title] => 'Semiconductor circuit having buffer function' [patent_app_type] => 1 [patent_app_number] => 7/354757 [patent_app_country] => US [patent_app_date] => 1989-05-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 1665 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 292 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/006/05006732.pdf [firstpage_image] =>[orig_patent_app_number] => 354757 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/354757
Semiconductor circuit having buffer function May 21, 1989 Issued
Array ( [id] => 2736767 [patent_doc_number] => 05032739 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-07-16 [patent_title] => 'Input selection circuit using a plurality of bidirectional analogue switches' [patent_app_type] => 1 [patent_app_number] => 7/353483 [patent_app_country] => US [patent_app_date] => 1989-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 2512 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 228 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/032/05032739.pdf [firstpage_image] =>[orig_patent_app_number] => 353483 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/353483
Input selection circuit using a plurality of bidirectional analogue switches May 17, 1989 Issued
Array ( [id] => 2593734 [patent_doc_number] => 04959557 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-09-25 [patent_title] => 'Negative feedback circuit to control the duty cycle of a logic system clock' [patent_app_type] => 1 [patent_app_number] => 7/354227 [patent_app_country] => US [patent_app_date] => 1989-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 10 [patent_no_of_words] => 3780 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/959/04959557.pdf [firstpage_image] =>[orig_patent_app_number] => 354227 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/354227
Negative feedback circuit to control the duty cycle of a logic system clock May 17, 1989 Issued
Array ( [id] => 2630059 [patent_doc_number] => 04950924 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-08-21 [patent_title] => 'High speed noise immune bipolar logic family' [patent_app_type] => 1 [patent_app_number] => 7/350193 [patent_app_country] => US [patent_app_date] => 1989-05-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 2825 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 259 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/950/04950924.pdf [firstpage_image] =>[orig_patent_app_number] => 350193 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/350193
High speed noise immune bipolar logic family May 10, 1989 Issued
07/349102 ELECTRONICALLY CONTROLLED VARIABLE GAIN AMPLIFIER May 8, 1989 Abandoned
Array ( [id] => 2659681 [patent_doc_number] => 04972102 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-11-20 [patent_title] => 'Single-ended sense amplifier with dual feedback and a latching disable mode that saves power' [patent_app_type] => 1 [patent_app_number] => 7/348927 [patent_app_country] => US [patent_app_date] => 1989-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 4415 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/972/04972102.pdf [firstpage_image] =>[orig_patent_app_number] => 348927 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/348927
Single-ended sense amplifier with dual feedback and a latching disable mode that saves power May 7, 1989 Issued
Array ( [id] => 2691466 [patent_doc_number] => 05049767 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1991-09-17 [patent_title] => 'Shared inverter outputs delay system' [patent_app_type] => 1 [patent_app_number] => 7/345926 [patent_app_country] => US [patent_app_date] => 1989-05-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 2565 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 461 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/049/05049767.pdf [firstpage_image] =>[orig_patent_app_number] => 345926 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/345926
Shared inverter outputs delay system Apr 30, 1989 Issued
Array ( [id] => 2659567 [patent_doc_number] => 04972097 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1990-11-20 [patent_title] => 'Reference voltage generating circuit in semiconductor device' [patent_app_type] => 1 [patent_app_number] => 7/340910 [patent_app_country] => US [patent_app_date] => 1989-04-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 3 [patent_no_of_words] => 1325 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/972/04972097.pdf [firstpage_image] =>[orig_patent_app_number] => 340910 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/340910
Reference voltage generating circuit in semiconductor device Apr 19, 1989 Issued
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