
Tesfaldet Bocure
Examiner (ID: 9273, Phone: (571)272-3015 , Office: P/2634 )
| Most Active Art Unit | 2611 |
| Art Unit(s) | 2611, 2614, 2731, 0, 2631, 2634, 2633, 2603 |
| Total Applications | 2324 |
| Issued Applications | 2050 |
| Pending Applications | 117 |
| Abandoned Applications | 162 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
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[id] => 12263735
[patent_doc_number] => 20180082931
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[patent_kind] => A1
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[patent_title] => 'LEAD FRAME AND ELECTRONIC COMPONENT DEVICE'
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[patent_app_number] => 15/701507
[patent_app_country] => US
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Array
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[patent_issue_date] => 2018-08-07
[patent_title] => Dynamic random access memory and method of fabricating the same
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Array
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[patent_title] => 'DISPLAY PANEL WITH DAM STRUCTURE'
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Array
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[patent_issue_date] => 2017-11-02
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[rel_patent_id] =>[rel_patent_doc_number] =>) 15/650677 | Optoelectronic semiconductor chip | Jul 13, 2017 | Issued |
Array
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[id] => 12498657
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[patent_title] => Package including a plurality of stacked semiconductor devices having area efficient ESD protection
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Array
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[patent_issue_date] => 2018-08-21
[patent_title] => Display apparatus and pixel structure thereof
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Array
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[patent_title] => 'AREA SENSOR AND DISPLAY APPARATUS PROVIDED WITH AN AREA SENSOR'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 15/641556 | Area sensor and display apparatus provided with an area sensor | Jul 4, 2017 | Issued |
Array
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[id] => 12141246
[patent_doc_number] => 20180019329
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[patent_issue_date] => 2018-01-18
[patent_title] => 'BIPOLAR TRANSISTOR ON HIGH-RESISTIVITY SUBSTRATE'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 15/634827 | Semiconductor die fabrication methods | Jun 26, 2017 | Issued |
Array
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[id] => 13705075
[patent_doc_number] => 20170363492
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[patent_issue_date] => 2017-12-21
[patent_title] => SEMICONDUCTOR SENSOR ASSEMBLY FOR HARSH MEDIA APPLICATION
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[rel_patent_id] =>[rel_patent_doc_number] =>) 15/628758 | Semiconductor sensor assembly for harsh media application | Jun 20, 2017 | Issued |
Array
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[id] => 11946096
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[patent_title] => 'VERTICAL POWER TRANSISTOR WITH TERMINATION AREA HAVING DOPED TRENCHES WITH VARIABLE PITCHES'
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[patent_app_number] => 15/596994
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[rel_patent_id] =>[rel_patent_doc_number] =>) 15/596994 | Vertical power transistor with termination area having doped trenches with variable pitches | May 15, 2017 | Issued |
Array
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[id] => 12314895
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[patent_issue_date] => 2018-04-10
[patent_title] => Vertical power transistor with deep trenches and deep regions surrounding cell array
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Array
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[rel_patent_id] =>[rel_patent_doc_number] =>) 15/499132 | Method for manufacturing imaging apparatus, and imaging apparatus | Apr 26, 2017 | Issued |
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