Search

Thai Q. Phan

Examiner (ID: 12245, Phone: (571)272-3783 , Office: P/2128 )

Most Active Art Unit
2128
Art Unit(s)
2128, 2123, 2304, 2763, 2147
Total Applications
1608
Issued Applications
1367
Pending Applications
67
Abandoned Applications
183

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 593646 [patent_doc_number] => 07457738 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-11-25 [patent_title] => 'Method for decoding instruction in architectural simulator' [patent_app_type] => utility [patent_app_number] => 11/081997 [patent_app_country] => US [patent_app_date] => 2005-03-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 1800 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/457/07457738.pdf [firstpage_image] =>[orig_patent_app_number] => 11081997 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/081997
Method for decoding instruction in architectural simulator Mar 15, 2005 Issued
Array ( [id] => 6960994 [patent_doc_number] => 20050216246 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-09-29 [patent_title] => 'Device characterization concept' [patent_app_type] => utility [patent_app_number] => 11/081084 [patent_app_country] => US [patent_app_date] => 2005-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3042 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0216/20050216246.pdf [firstpage_image] =>[orig_patent_app_number] => 11081084 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/081084
Device characterization concept Mar 14, 2005 Abandoned
Array ( [id] => 5787822 [patent_doc_number] => 20060206296 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-09-14 [patent_title] => 'Device and method for simulating communication system capable of easily controlling protocol message' [patent_app_type] => utility [patent_app_number] => 10/551953 [patent_app_country] => US [patent_app_date] => 2005-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 14362 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0206/20060206296.pdf [firstpage_image] =>[orig_patent_app_number] => 10551953 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/551953
Device and method for simulating communication system capable of easily controlling protocol message Feb 27, 2005 Issued
Array ( [id] => 37427 [patent_doc_number] => 07788078 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-08-31 [patent_title] => 'Processor/memory co-exploration at multiple abstraction levels' [patent_app_type] => utility [patent_app_number] => 11/069496 [patent_app_country] => US [patent_app_date] => 2005-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6998 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/788/07788078.pdf [firstpage_image] =>[orig_patent_app_number] => 11069496 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/069496
Processor/memory co-exploration at multiple abstraction levels Feb 27, 2005 Issued
Array ( [id] => 596693 [patent_doc_number] => 07451067 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-11-11 [patent_title] => 'Method for analysis of cell structure, and cell structure' [patent_app_type] => utility [patent_app_number] => 11/066241 [patent_app_country] => US [patent_app_date] => 2005-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 37 [patent_no_of_words] => 9855 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 272 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/451/07451067.pdf [firstpage_image] =>[orig_patent_app_number] => 11066241 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/066241
Method for analysis of cell structure, and cell structure Feb 24, 2005 Issued
Array ( [id] => 816072 [patent_doc_number] => 07415403 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-08-19 [patent_title] => 'Systems and methods for efficiently simulating analog behavior of designs having hierarchical structure' [patent_app_type] => utility [patent_app_number] => 11/058859 [patent_app_country] => US [patent_app_date] => 2005-02-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 22 [patent_no_of_words] => 39499 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/415/07415403.pdf [firstpage_image] =>[orig_patent_app_number] => 11058859 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/058859
Systems and methods for efficiently simulating analog behavior of designs having hierarchical structure Feb 14, 2005 Issued
Array ( [id] => 929491 [patent_doc_number] => 07315803 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2008-01-01 [patent_title] => 'Verification environment creation infrastructure for bus-based systems and modules' [patent_app_type] => utility [patent_app_number] => 11/055275 [patent_app_country] => US [patent_app_date] => 2005-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3389 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/315/07315803.pdf [firstpage_image] =>[orig_patent_app_number] => 11055275 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/055275
Verification environment creation infrastructure for bus-based systems and modules Feb 9, 2005 Issued
Array ( [id] => 5815845 [patent_doc_number] => 20060085178 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-04-20 [patent_title] => 'Apparatus and method for modeling and analyzing network simulation for network simulation package' [patent_app_type] => utility [patent_app_number] => 11/051667 [patent_app_country] => US [patent_app_date] => 2005-02-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6036 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0085/20060085178.pdf [firstpage_image] =>[orig_patent_app_number] => 11051667 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/051667
Apparatus and method for modeling and analyzing network simulation for network simulation package Feb 3, 2005 Issued
Array ( [id] => 4699677 [patent_doc_number] => 20080221861 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-09-11 [patent_title] => 'Verification Apparatus and Verification Method' [patent_app_type] => utility [patent_app_number] => 10/586620 [patent_app_country] => US [patent_app_date] => 2005-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 29 [patent_no_of_words] => 15377 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0221/20080221861.pdf [firstpage_image] =>[orig_patent_app_number] => 10586620 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/586620
Verification Apparatus and Verification Method Jan 17, 2005 Abandoned
Array ( [id] => 587956 [patent_doc_number] => 07464009 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-12-09 [patent_title] => 'Systems, methods, and articles of manufacture for flexible path optimization' [patent_app_type] => utility [patent_app_number] => 11/025053 [patent_app_country] => US [patent_app_date] => 2004-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 7378 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 193 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/464/07464009.pdf [firstpage_image] =>[orig_patent_app_number] => 11025053 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/025053
Systems, methods, and articles of manufacture for flexible path optimization Dec 29, 2004 Issued
Array ( [id] => 7600282 [patent_doc_number] => 07386428 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2008-06-10 [patent_title] => 'Method and system for guided cable contact in finite element analysis' [patent_app_type] => utility [patent_app_number] => 11/025198 [patent_app_country] => US [patent_app_date] => 2004-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 6523 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/386/07386428.pdf [firstpage_image] =>[orig_patent_app_number] => 11025198 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/025198
Method and system for guided cable contact in finite element analysis Dec 28, 2004 Issued
Array ( [id] => 320642 [patent_doc_number] => 07523023 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2009-04-21 [patent_title] => 'Automatic generation of component interfaces for computational hardware implementations generated from a block diagram model' [patent_app_type] => utility [patent_app_number] => 11/021760 [patent_app_country] => US [patent_app_date] => 2004-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 15924 [patent_no_of_claims] => 68 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/523/07523023.pdf [firstpage_image] =>[orig_patent_app_number] => 11021760 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/021760
Automatic generation of component interfaces for computational hardware implementations generated from a block diagram model Dec 22, 2004 Issued
Array ( [id] => 5915071 [patent_doc_number] => 20060129395 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-06-15 [patent_title] => 'Gradient learning for probabilistic ARMA time-series models' [patent_app_type] => utility [patent_app_number] => 11/011864 [patent_app_country] => US [patent_app_date] => 2004-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 8577 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0129/20060129395.pdf [firstpage_image] =>[orig_patent_app_number] => 11011864 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/011864
Gradient learning for probabilistic ARMA time-series models Dec 13, 2004 Issued
Array ( [id] => 7006433 [patent_doc_number] => 20050171746 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-08-04 [patent_title] => 'Network models of complex systems' [patent_app_type] => utility [patent_app_number] => 11/004108 [patent_app_country] => US [patent_app_date] => 2004-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 42 [patent_figures_cnt] => 42 [patent_no_of_words] => 74582 [patent_no_of_claims] => 43 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0171/20050171746.pdf [firstpage_image] =>[orig_patent_app_number] => 11004108 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/004108
Network models of complex systems Dec 4, 2004 Abandoned
Array ( [id] => 5847116 [patent_doc_number] => 20060123272 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-06-08 [patent_title] => 'Scoring mechanism for automatically generated test programs' [patent_app_type] => utility [patent_app_number] => 11/002991 [patent_app_country] => US [patent_app_date] => 2004-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4376 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0123/20060123272.pdf [firstpage_image] =>[orig_patent_app_number] => 11002991 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/002991
Scoring mechanism for automatically generated test programs Dec 2, 2004 Issued
Array ( [id] => 411048 [patent_doc_number] => 07286971 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-10-23 [patent_title] => 'System and method for efficiently visualizing and comparing communication network system performance' [patent_app_type] => utility [patent_app_number] => 10/956027 [patent_app_country] => US [patent_app_date] => 2004-10-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 12584 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/286/07286971.pdf [firstpage_image] =>[orig_patent_app_number] => 10956027 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/956027
System and method for efficiently visualizing and comparing communication network system performance Oct 3, 2004 Issued
Array ( [id] => 7084459 [patent_doc_number] => 20050049839 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-03-03 [patent_title] => 'Methods of forming radiation-patterning tools; carrier waves and computer readable media' [patent_app_type] => utility [patent_app_number] => 10/953982 [patent_app_country] => US [patent_app_date] => 2004-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 5732 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0049/20050049839.pdf [firstpage_image] =>[orig_patent_app_number] => 10953982 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/953982
Methods of forming radiation-patterning tools; carrier waves and computer readable media Sep 27, 2004 Issued
Array ( [id] => 839407 [patent_doc_number] => 07395197 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-07-01 [patent_title] => 'Verification method and system for logic circuit' [patent_app_type] => utility [patent_app_number] => 10/935270 [patent_app_country] => US [patent_app_date] => 2004-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3541 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/395/07395197.pdf [firstpage_image] =>[orig_patent_app_number] => 10935270 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/935270
Verification method and system for logic circuit Sep 7, 2004 Issued
Array ( [id] => 5829846 [patent_doc_number] => 20060064178 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-03-23 [patent_title] => 'System, method and computer program product for developing a system-of-systems architecture model' [patent_app_type] => utility [patent_app_number] => 10/935355 [patent_app_country] => US [patent_app_date] => 2004-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 21939 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0064/20060064178.pdf [firstpage_image] =>[orig_patent_app_number] => 10935355 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/935355
System, method and computer program product for developing a system-of-systems architecture model Sep 6, 2004 Issued
Array ( [id] => 5905677 [patent_doc_number] => 20060047495 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-03-02 [patent_title] => 'Analyzer for spawning pairs in speculative multithreaded processor' [patent_app_type] => utility [patent_app_number] => 10/933076 [patent_app_country] => US [patent_app_date] => 2004-09-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 13488 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0047/20060047495.pdf [firstpage_image] =>[orig_patent_app_number] => 10933076 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/933076
Analyzer for spawning pairs in speculative multithreaded processor Aug 31, 2004 Abandoned
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