Thai Q. Phan

Array ( [id] => 7443333 [patent_doc_number] => 20040003020 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-01-01 [patent_title] => 'Time-indexed multiplexing as an efficient method of scheduling in hardware' [patent_app_type] => new [patent_app_number] => 10/139644 [patent_app_country] => US [patent_app_date] => 2002-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 6341 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0003/20040003020.pdf [firstpage_image] =>[orig_patent_app_number] => 10139644 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6726037 [patent_doc_number] => 20030208349 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-11-06 [patent_title] => 'Minimizing event scheduling overhead in VHDL simulation' [patent_app_type] => new [patent_app_number] => 10/063627 [patent_app_country] => US [patent_app_date] => 2002-05-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1387 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0208/20030208349.pdf [firstpage_image] =>[orig_patent_app_number] => 10063627 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6726034 [patent_doc_number] => 20030208346 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-11-06 [patent_title] => 'Block characterization of RC network using AWE(asymptotic waveform evaluation)' [patent_app_type] => new [patent_app_number] => 10/063625 [patent_app_country] => US [patent_app_date] => 2002-05-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 922 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 248 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0208/20030208346.pdf [firstpage_image] =>[orig_patent_app_number] => 10063625 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5847745 [patent_doc_number] => 20020133394 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-09-19 [patent_title] => 'Method for categorizing, describing and modeling types of system users' [patent_app_type] => new [patent_app_number] => 10/134430 [patent_app_country] => US [patent_app_date] => 2002-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 13564 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0133/20020133394.pdf [firstpage_image] =>[orig_patent_app_number] => 10134430 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 744046 [patent_doc_number] => 07035778 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-04-25 [patent_title] => 'Method of assaying downhole occurrences and conditions' [patent_app_type] => utility [patent_app_number] => 10/133078 [patent_app_country] => US [patent_app_date] => 2002-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 15 [patent_no_of_words] => 18498 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 19 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/035/07035778.pdf [firstpage_image] =>[orig_patent_app_number] => 10133078 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6546774 [patent_doc_number] => 20020193977 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-12-19 [patent_title] => 'Method and apparatus for simulating electronic circuits having conductor or dielectric losses' [patent_app_type] => new [patent_app_number] => 10/117734 [patent_app_country] => US [patent_app_date] => 2002-04-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3399 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 16 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0193/20020193977.pdf [firstpage_image] =>[orig_patent_app_number] => 10117734 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 700565 [patent_doc_number] => 07072823 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-07-04 [patent_title] => 'Method and apparatus for accessing memory using Ethernet packets' [patent_app_type] => utility [patent_app_number] => 10/113332 [patent_app_country] => US [patent_app_date] => 2002-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 4279 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/072/07072823.pdf [firstpage_image] =>[orig_patent_app_number] => 10113332 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 615320 [patent_doc_number] => 07149678 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-12-12 [patent_title] => 'High level executable network abstract machine' [patent_app_type] => utility [patent_app_number] => 10/112319 [patent_app_country] => US [patent_app_date] => 2002-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 9700 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/149/07149678.pdf [firstpage_image] =>[orig_patent_app_number] => 10112319 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7366274 [patent_doc_number] => 20040015464 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-01-22 [patent_title] => 'Method and computer program product for producing a pattern recognition training set' [patent_app_type] => new [patent_app_number] => 10/105714 [patent_app_country] => US [patent_app_date] => 2002-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3992 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0015/20040015464.pdf [firstpage_image] =>[orig_patent_app_number] => 10105714 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6712157 [patent_doc_number] => 20030171906 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-09-11 [patent_title] => 'Method for transforming stand-alone verification tests for an embedded block into serial scan test patterns for detecting manufacturing defects' [patent_app_type] => new [patent_app_number] => 10/094885 [patent_app_country] => US [patent_app_date] => 2002-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 4126 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0171/20030171906.pdf [firstpage_image] =>[orig_patent_app_number] => 10094885 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 622797 [patent_doc_number] => 07143023 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-11-28 [patent_title] => 'System and method of describing signal transfers and using same to automate the simulation and analysis of a circuit or system design' [patent_app_type] => utility [patent_app_number] => 10/087297 [patent_app_country] => US [patent_app_date] => 2002-03-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 13 [patent_no_of_words] => 6902 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/143/07143023.pdf [firstpage_image] =>[orig_patent_app_number] => 10087297 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6256237 [patent_doc_number] => 20020186248 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-12-12 [patent_title] => 'Method and apparatus for pattern based generation of graphical user interfaces (GUI)' [patent_app_type] => new [patent_app_number] => 10/078964 [patent_app_country] => US [patent_app_date] => 2002-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3259 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0186/20020186248.pdf [firstpage_image] =>[orig_patent_app_number] => 10078964 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 537403 [patent_doc_number] => 07188059 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-03-06 [patent_title] => 'System and method for operating software in a flight simulator environment' [patent_app_type] => utility [patent_app_number] => 10/080196 [patent_app_country] => US [patent_app_date] => 2002-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 16 [patent_no_of_words] => 5749 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/188/07188059.pdf [firstpage_image] =>[orig_patent_app_number] => 10080196 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7678671 [patent_doc_number] => 20030195665 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-10-16 [patent_title] => 'Method for removal of PID dynamics from MPC models' [patent_app_type] => new [patent_app_number] => 10/043473 [patent_app_country] => US [patent_app_date] => 2002-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 15870 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0195/20030195665.pdf [firstpage_image] =>[orig_patent_app_number] => 10043473 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6762561 [patent_doc_number] => 20030125923 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-07-03 [patent_title] => 'Simulation of di/dt-induced power supply voltage variation' [patent_app_type] => new [patent_app_number] => 10/041062 [patent_app_country] => US [patent_app_date] => 2001-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 7975 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0125/20030125923.pdf [firstpage_image] =>[orig_patent_app_number] => 10041062 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6762457 [patent_doc_number] => 20030125819 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-07-03 [patent_title] => 'Control loop status maintainer for temporarily opened control loops' [patent_app_type] => new [patent_app_number] => 10/033566 [patent_app_country] => US [patent_app_date] => 2001-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3560 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 268 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0125/20030125819.pdf [firstpage_image] =>[orig_patent_app_number] => 10033566 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6084128 [patent_doc_number] => 20020082815 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-06-27 [patent_title] => 'Method for forming an optimized neural network module intended to simulate the flow mode of a multiphase fluid stream' [patent_app_type] => new [patent_app_number] => 10/024719 [patent_app_country] => US [patent_app_date] => 2001-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2474 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0082/20020082815.pdf [firstpage_image] =>[orig_patent_app_number] => 10024719 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1039751 [patent_doc_number] => 06873943 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-03-29 [patent_title] => 'Method and system of vectorial cartography' [patent_app_type] => utility [patent_app_number] => 10/020965 [patent_app_country] => US [patent_app_date] => 2001-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 5325 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/873/06873943.pdf [firstpage_image] =>[orig_patent_app_number] => 10020965 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6655855 [patent_doc_number] => 20030106030 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-06-05 [patent_title] => 'Method and program product for compressing an electronic circuit model' [patent_app_type] => new [patent_app_number] => 09/998174 [patent_app_country] => US [patent_app_date] => 2001-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4857 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0106/20030106030.pdf [firstpage_image] =>[orig_patent_app_number] => 09998174 [rel_patent_id] =>[rel_patent_doc_number] =>)