Search

Than Vinh Nguyen

Examiner (ID: 9136)

Most Active Art Unit
2138
Art Unit(s)
2138, 2787, 2759, 2188, 2309, 2751, 2187
Total Applications
1830
Issued Applications
1628
Pending Applications
77
Abandoned Applications
148

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18198914 [patent_doc_number] => 20230052433 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-02-16 [patent_title] => ACCELERATOR TO REDUCE DATA DIMENSIONALITY AND ASSOCIATED SYSTEMS AND METHODS [patent_app_type] => utility [patent_app_number] => 17/571440 [patent_app_country] => US [patent_app_date] => 2022-01-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19486 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17571440 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/571440
Accelerator to reduce data dimensionality and associated systems and methods Jan 6, 2022 Issued
Array ( [id] => 18224574 [patent_doc_number] => 20230063568 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-02 [patent_title] => IMPLEMENTING COMPILER-BASED MEMORY SAFETY FOR A GRAPHIC PROCESSING UNIT [patent_app_type] => utility [patent_app_number] => 17/565352 [patent_app_country] => US [patent_app_date] => 2021-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13511 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17565352 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/565352
Implementing compiler-based memory safety for a graphic processing unit Dec 28, 2021 Issued
Array ( [id] => 17550042 [patent_doc_number] => 20220121384 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-04-21 [patent_title] => Hot Data Management Method, Apparatus, and System [patent_app_type] => utility [patent_app_number] => 17/563553 [patent_app_country] => US [patent_app_date] => 2021-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 20434 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17563553 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/563553
Hot data migration method, apparatus, and system Dec 27, 2021 Issued
Array ( [id] => 17690223 [patent_doc_number] => 20220197516 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-23 [patent_title] => TAPE LIBRARY EMULATION WITH AUTOMATIC CONFIGURATION AND DATA RETENTION [patent_app_type] => utility [patent_app_number] => 17/562879 [patent_app_country] => US [patent_app_date] => 2021-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4680 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => 0 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17562879 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/562879
Tape library emulation with automatic configuration and data retention Dec 26, 2021 Issued
Array ( [id] => 17535301 [patent_doc_number] => 20220113910 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-04-14 [patent_title] => MEMORY SYSTEM AND METHOD OF CONTROLLING NONVOLATILE MEMORY [patent_app_type] => utility [patent_app_number] => 17/557148 [patent_app_country] => US [patent_app_date] => 2021-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18631 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 337 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17557148 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/557148
Memory system and method of controlling nonvolatile memory Dec 20, 2021 Issued
Array ( [id] => 19045586 [patent_doc_number] => 11934698 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-03-19 [patent_title] => Process isolation for a processor-in-memory ("PIM") device [patent_app_type] => utility [patent_app_number] => 17/556503 [patent_app_country] => US [patent_app_date] => 2021-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 8228 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17556503 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/556503
Process isolation for a processor-in-memory ("PIM") device Dec 19, 2021 Issued
Array ( [id] => 17613900 [patent_doc_number] => 20220156180 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-05-19 [patent_title] => SECURITY CHECK SYSTEMS AND METHODS FOR MEMORY ALLOCATIONS [patent_app_type] => utility [patent_app_number] => 17/539933 [patent_app_country] => US [patent_app_date] => 2021-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9303 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17539933 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/539933
Security check systems and methods for memory allocations Nov 30, 2021 Issued
Array ( [id] => 18803197 [patent_doc_number] => 11836355 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-12-05 [patent_title] => Systems and methods for resetting a degraded storage resource [patent_app_type] => utility [patent_app_number] => 17/524995 [patent_app_country] => US [patent_app_date] => 2021-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3115 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17524995 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/524995
Systems and methods for resetting a degraded storage resource Nov 20, 2021 Issued
Array ( [id] => 18918019 [patent_doc_number] => 11880298 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-01-23 [patent_title] => Allocation of memory within a data type-specific memory heap [patent_app_type] => utility [patent_app_number] => 17/529225 [patent_app_country] => US [patent_app_date] => 2021-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 18 [patent_no_of_words] => 10595 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17529225 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/529225
Allocation of memory within a data type-specific memory heap Nov 16, 2021 Issued
Array ( [id] => 17446188 [patent_doc_number] => 20220066693 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-03 [patent_title] => SYSTEM AND METHOD OF WRITING TO NONVOLATILE MEMORY USING WRITE BUFFERS [patent_app_type] => utility [patent_app_number] => 17/523415 [patent_app_country] => US [patent_app_date] => 2021-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11968 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17523415 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/523415
System and method of writing to nonvolatile memory using write buffers Nov 9, 2021 Issued
Array ( [id] => 17659324 [patent_doc_number] => 20220179789 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-09 [patent_title] => METHOD AND APPARATUS FOR UNIFORM MEMORY ACCESS IN A STORAGE CLUSTER [patent_app_type] => utility [patent_app_number] => 17/522705 [patent_app_country] => US [patent_app_date] => 2021-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5589 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => 0 [patent_words_short_claim] => 219 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17522705 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/522705
Uniform memory access in a system having a plurality of nodes Nov 8, 2021 Issued
Array ( [id] => 18493309 [patent_doc_number] => 11698725 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-07-11 [patent_title] => Apparatuses and methods for concurrently accessing multiple memory planes of a memory during a memory access operation [patent_app_type] => utility [patent_app_number] => 17/452468 [patent_app_country] => US [patent_app_date] => 2021-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7954 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 183 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17452468 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/452468
Apparatuses and methods for concurrently accessing multiple memory planes of a memory during a memory access operation Oct 26, 2021 Issued
Array ( [id] => 18320027 [patent_doc_number] => 20230118155 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-04-20 [patent_title] => RESOURCE ALLOCATION TECHNIQUES USING A METADATA LOG [patent_app_type] => utility [patent_app_number] => 17/502103 [patent_app_country] => US [patent_app_date] => 2021-10-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 31371 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17502103 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/502103
Resource allocation techniques using a metadata log Oct 14, 2021 Issued
Array ( [id] => 18087182 [patent_doc_number] => 11537314 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-12-27 [patent_title] => Resynchronization of individual volumes of a consistency group (CG) within a cross-site storage solution while maintaining synchronization of other volumes of the CG [patent_app_type] => utility [patent_app_number] => 17/495990 [patent_app_country] => US [patent_app_date] => 2021-10-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 13687 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 191 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17495990 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/495990
Resynchronization of individual volumes of a consistency group (CG) within a cross-site storage solution while maintaining synchronization of other volumes of the CG Oct 6, 2021 Issued
Array ( [id] => 18287528 [patent_doc_number] => 20230103000 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-30 [patent_title] => HARDWARE MANAGED ADDRESS TRANSLATION SERVICE FOR INTEGRATED DEVICES [patent_app_type] => utility [patent_app_number] => 17/485386 [patent_app_country] => US [patent_app_date] => 2021-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9579 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17485386 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/485386
HARDWARE MANAGED ADDRESS TRANSLATION SERVICE FOR INTEGRATED DEVICES Sep 24, 2021 Abandoned
Array ( [id] => 18287528 [patent_doc_number] => 20230103000 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-30 [patent_title] => HARDWARE MANAGED ADDRESS TRANSLATION SERVICE FOR INTEGRATED DEVICES [patent_app_type] => utility [patent_app_number] => 17/485386 [patent_app_country] => US [patent_app_date] => 2021-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9579 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17485386 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/485386
HARDWARE MANAGED ADDRESS TRANSLATION SERVICE FOR INTEGRATED DEVICES Sep 24, 2021 Abandoned
Array ( [id] => 18287528 [patent_doc_number] => 20230103000 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-30 [patent_title] => HARDWARE MANAGED ADDRESS TRANSLATION SERVICE FOR INTEGRATED DEVICES [patent_app_type] => utility [patent_app_number] => 17/485386 [patent_app_country] => US [patent_app_date] => 2021-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9579 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17485386 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/485386
HARDWARE MANAGED ADDRESS TRANSLATION SERVICE FOR INTEGRATED DEVICES Sep 24, 2021 Abandoned
Array ( [id] => 19811359 [patent_doc_number] => 12242753 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-03-04 [patent_title] => Reduced network load with combined put or get and receiver-managed offset [patent_app_type] => utility [patent_app_number] => 17/485114 [patent_app_country] => US [patent_app_date] => 2021-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 15 [patent_no_of_words] => 7664 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17485114 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/485114
Reduced network load with combined put or get and receiver-managed offset Sep 23, 2021 Issued
Array ( [id] => 18548046 [patent_doc_number] => 11721404 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-08-08 [patent_title] => Operation of mixed mode blocks [patent_app_type] => utility [patent_app_number] => 17/484777 [patent_app_country] => US [patent_app_date] => 2021-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 5143 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17484777 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/484777
Operation of mixed mode blocks Sep 23, 2021 Issued
Array ( [id] => 18228582 [patent_doc_number] => 20230067576 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-02 [patent_title] => REQUEST CONTROL FOR MEMORY SUB-SYSTEMS [patent_app_type] => utility [patent_app_number] => 17/461701 [patent_app_country] => US [patent_app_date] => 2021-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10491 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17461701 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/461701
Request control for memory sub-systems Aug 29, 2021 Issued
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