Search

Than Vinh Nguyen

Examiner (ID: 3446, Phone: (571)272-4198 , Office: P/2138 )

Most Active Art Unit
2138
Art Unit(s)
2188, 2138, 2187, 2787, 2759, 2309, 2751
Total Applications
1861
Issued Applications
1652
Pending Applications
79
Abandoned Applications
148

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17164942 [patent_doc_number] => 11151040 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-10-19 [patent_title] => Approximate cache memory [patent_app_type] => utility [patent_app_number] => 16/362672 [patent_app_country] => US [patent_app_date] => 2019-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7886 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16362672 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/362672
Approximate cache memory Mar 23, 2019 Issued
Array ( [id] => 17194703 [patent_doc_number] => 11163456 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-11-02 [patent_title] => Using mirror indicators to determine whether to mirror tracks in a data set in a primary volume mirrored to a secondary volume [patent_app_type] => utility [patent_app_number] => 16/352818 [patent_app_country] => US [patent_app_date] => 2019-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 12 [patent_no_of_words] => 6349 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16352818 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/352818
Using mirror indicators to determine whether to mirror tracks in a data set in a primary volume mirrored to a secondary volume Mar 12, 2019 Issued
Array ( [id] => 17454655 [patent_doc_number] => 11269514 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-03-08 [patent_title] => Memory fabric software implementation [patent_app_type] => utility [patent_app_number] => 16/269833 [patent_app_country] => US [patent_app_date] => 2019-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 36 [patent_figures_cnt] => 36 [patent_no_of_words] => 34196 [patent_no_of_claims] => 41 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 189 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16269833 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/269833
Memory fabric software implementation Feb 6, 2019 Issued
Array ( [id] => 16208804 [patent_doc_number] => 20200241794 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-07-30 [patent_title] => LOW LATENCY SWAP DEVICE, SYSTEM AND METHOD [patent_app_type] => utility [patent_app_number] => 16/256977 [patent_app_country] => US [patent_app_date] => 2019-01-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8342 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16256977 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/256977
LOW LATENCY SWAP DEVICE, SYSTEM AND METHOD Jan 23, 2019 Abandoned
Array ( [id] => 14585209 [patent_doc_number] => 20190220213 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-07-18 [patent_title] => METHOD, DEVICE AND COMPUTER PROGRAM PRODUCT FOR CHANGING TYPE OF STORAGE SYSTEM [patent_app_type] => utility [patent_app_number] => 16/248015 [patent_app_country] => US [patent_app_date] => 2019-01-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6618 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16248015 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/248015
Method, device and computer program product for changing type of storage system Jan 14, 2019 Issued
Array ( [id] => 16501355 [patent_doc_number] => 10866738 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-12-15 [patent_title] => Performance attributes for memory [patent_app_type] => utility [patent_app_number] => 16/247318 [patent_app_country] => US [patent_app_date] => 2019-01-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 5065 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16247318 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/247318
Performance attributes for memory Jan 13, 2019 Issued
Array ( [id] => 16501522 [patent_doc_number] => 10866907 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-12-15 [patent_title] => Eviction prioritization for image processing [patent_app_type] => utility [patent_app_number] => 16/242912 [patent_app_country] => US [patent_app_date] => 2019-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 11154 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16242912 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/242912
Eviction prioritization for image processing Jan 7, 2019 Issued
Array ( [id] => 15981921 [patent_doc_number] => 10671288 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-06-02 [patent_title] => Hierarchical sparse tensor compression method in artificial intelligent devices [patent_app_type] => utility [patent_app_number] => 16/237616 [patent_app_country] => US [patent_app_date] => 2018-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3565 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 245 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16237616 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/237616
Hierarchical sparse tensor compression method in artificial intelligent devices Dec 30, 2018 Issued
Array ( [id] => 14282345 [patent_doc_number] => 20190138457 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-05-09 [patent_title] => UNIFIED HARDWARE AND SOFTWARE TWO-LEVEL MEMORY [patent_app_type] => utility [patent_app_number] => 16/235504 [patent_app_country] => US [patent_app_date] => 2018-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14279 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 321 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16235504 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/235504
Unified hardware and software two-level memory Dec 27, 2018 Issued
Array ( [id] => 15440231 [patent_doc_number] => 20200034299 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-01-30 [patent_title] => MEMORY SYSTEM AND METHOD FOR OPERATING THE SAME [patent_app_type] => utility [patent_app_number] => 16/227737 [patent_app_country] => US [patent_app_date] => 2018-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11907 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16227737 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/227737
Method and apparatus for migrating data between nonvolatile main memory and first or second caches Dec 19, 2018 Issued
Array ( [id] => 14585201 [patent_doc_number] => 20190220209 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-07-18 [patent_title] => INFORMATION PROCESSING APPARATUS, METHOD FOR CONTROL, AND NON-TRANSITORY COMPUTER-READABLE RECORDING MEDIUM HAVING STORED THEREIN CONTROL PROGRAM [patent_app_type] => utility [patent_app_number] => 16/226710 [patent_app_country] => US [patent_app_date] => 2018-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7513 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16226710 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/226710
INFORMATION PROCESSING APPARATUS, METHOD FOR CONTROL, AND NON-TRANSITORY COMPUTER-READABLE RECORDING MEDIUM HAVING STORED THEREIN CONTROL PROGRAM Dec 19, 2018 Abandoned
Array ( [id] => 16080157 [patent_doc_number] => 20200194065 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-06-18 [patent_title] => NON-VOLATILE STORAGE SYSTEM WITH REDUCED PROGRAM TRANSFERS [patent_app_type] => utility [patent_app_number] => 16/223716 [patent_app_country] => US [patent_app_date] => 2018-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12109 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16223716 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/223716
Non-volatile storage system with reduced program transfers Dec 17, 2018 Issued
Array ( [id] => 16462666 [patent_doc_number] => 10846014 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-11-24 [patent_title] => Concept for group memory write instructions [patent_app_type] => utility [patent_app_number] => 16/221743 [patent_app_country] => US [patent_app_date] => 2018-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 19 [patent_no_of_words] => 17736 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16221743 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/221743
Concept for group memory write instructions Dec 16, 2018 Issued
Array ( [id] => 16879706 [patent_doc_number] => 11029853 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-06-08 [patent_title] => Dynamic segment allocation for write requests by a storage system [patent_app_type] => utility [patent_app_number] => 16/222863 [patent_app_country] => US [patent_app_date] => 2018-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 10166 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16222863 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/222863
Dynamic segment allocation for write requests by a storage system Dec 16, 2018 Issued
Array ( [id] => 16064865 [patent_doc_number] => 10691378 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-06-23 [patent_title] => Data replication priority management [patent_app_type] => utility [patent_app_number] => 16/205761 [patent_app_country] => US [patent_app_date] => 2018-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 7596 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16205761 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/205761
Data replication priority management Nov 29, 2018 Issued
Array ( [id] => 16307483 [patent_doc_number] => 10776276 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-09-15 [patent_title] => Bypass storage class memory read cache based on a queue depth threshold [patent_app_type] => utility [patent_app_number] => 16/205742 [patent_app_country] => US [patent_app_date] => 2018-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 12545 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16205742 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/205742
Bypass storage class memory read cache based on a queue depth threshold Nov 29, 2018 Issued
Array ( [id] => 15997635 [patent_doc_number] => 20200174688 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-06-04 [patent_title] => COMBINED HARDWARE/SOFTWARE-ENFORCED SEGMENTATION OF MULTI-TENANT MEMORY/STORAGE SYSTEMS [patent_app_type] => utility [patent_app_number] => 16/205607 [patent_app_country] => US [patent_app_date] => 2018-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7982 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16205607 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/205607
Combined hardware/software-enforced segmentation of multi-tenant memory/storage systems Nov 29, 2018 Issued
Array ( [id] => 16307483 [patent_doc_number] => 10776276 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-09-15 [patent_title] => Bypass storage class memory read cache based on a queue depth threshold [patent_app_type] => utility [patent_app_number] => 16/205742 [patent_app_country] => US [patent_app_date] => 2018-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 12545 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16205742 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/205742
Bypass storage class memory read cache based on a queue depth threshold Nov 29, 2018 Issued
Array ( [id] => 16307483 [patent_doc_number] => 10776276 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-09-15 [patent_title] => Bypass storage class memory read cache based on a queue depth threshold [patent_app_type] => utility [patent_app_number] => 16/205742 [patent_app_country] => US [patent_app_date] => 2018-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 12545 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16205742 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/205742
Bypass storage class memory read cache based on a queue depth threshold Nov 29, 2018 Issued
Array ( [id] => 16307483 [patent_doc_number] => 10776276 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-09-15 [patent_title] => Bypass storage class memory read cache based on a queue depth threshold [patent_app_type] => utility [patent_app_number] => 16/205742 [patent_app_country] => US [patent_app_date] => 2018-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 12545 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16205742 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/205742
Bypass storage class memory read cache based on a queue depth threshold Nov 29, 2018 Issued
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