Search

Than Vinh Nguyen

Examiner (ID: 3446, Phone: (571)272-4198 , Office: P/2138 )

Most Active Art Unit
2138
Art Unit(s)
2188, 2138, 2187, 2787, 2759, 2309, 2751
Total Applications
1861
Issued Applications
1652
Pending Applications
79
Abandoned Applications
148

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 13017157 [patent_doc_number] => 10031693 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-07-24 [patent_title] => Optimizing off-loaded input/output (I/O) requests [patent_app_type] => utility [patent_app_number] => 15/720746 [patent_app_country] => US [patent_app_date] => 2017-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7304 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 415 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15720746 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/720746
Optimizing off-loaded input/output (I/O) requests Sep 28, 2017 Issued
Array ( [id] => 14135849 [patent_doc_number] => 20190102314 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-04-04 [patent_title] => TAG CACHE ADAPTIVE POWER GATING [patent_app_type] => utility [patent_app_number] => 15/721572 [patent_app_country] => US [patent_app_date] => 2017-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6494 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 29 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15721572 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/721572
TAG CACHE ADAPTIVE POWER GATING Sep 28, 2017 Abandoned
Array ( [id] => 12687871 [patent_doc_number] => 20180121123 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-05-03 [patent_title] => EFFICIENTLY TRAINING MEMORY DEVICE CHIP SELECT CONTROL [patent_app_type] => utility [patent_app_number] => 15/721516 [patent_app_country] => US [patent_app_date] => 2017-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15878 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15721516 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/721516
Efficiently training memory device chip select control Sep 28, 2017 Issued
Array ( [id] => 13069151 [patent_doc_number] => 10055355 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-08-21 [patent_title] => Non-disruptive clearing of varying address ranges from cache [patent_app_type] => utility [patent_app_number] => 15/716713 [patent_app_country] => US [patent_app_date] => 2017-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5665 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 203 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15716713 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/716713
Non-disruptive clearing of varying address ranges from cache Sep 26, 2017 Issued
Array ( [id] => 16446738 [patent_doc_number] => 10838665 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-11-17 [patent_title] => Method, device, and system for buffering data for read/write commands in NVME over fabric architecture [patent_app_type] => utility [patent_app_number] => 15/716791 [patent_app_country] => US [patent_app_date] => 2017-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 16192 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 226 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15716791 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/716791
Method, device, and system for buffering data for read/write commands in NVME over fabric architecture Sep 26, 2017 Issued
Array ( [id] => 13707141 [patent_doc_number] => 20170364525 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-12-21 [patent_title] => EFFICIENT SNAPSHOT MANAGEMENT IN A LARGE CAPACITY DISK ENVIRONMENT [patent_app_type] => utility [patent_app_number] => 15/690314 [patent_app_country] => US [patent_app_date] => 2017-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7790 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15690314 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/690314
Snapshot management using heatmaps in a large capacity disk environment Aug 29, 2017 Issued
Array ( [id] => 13860275 [patent_doc_number] => 10191857 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-01-29 [patent_title] => Machine learning for metadata cache management [patent_app_type] => utility [patent_app_number] => 15/682699 [patent_app_country] => US [patent_app_date] => 2017-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 9647 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 212 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15682699 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/682699
Machine learning for metadata cache management Aug 21, 2017 Issued
Array ( [id] => 12475155 [patent_doc_number] => 09990303 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-06-05 [patent_title] => Sharing data structures between processes by semi-invasive hybrid approach [patent_app_type] => utility [patent_app_number] => 15/682259 [patent_app_country] => US [patent_app_date] => 2017-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 9020 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 208 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15682259 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/682259
Sharing data structures between processes by semi-invasive hybrid approach Aug 20, 2017 Issued
Array ( [id] => 14061581 [patent_doc_number] => 10235083 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-03-19 [patent_title] => Systems and methods for efficiently moving data within a filesystem [patent_app_type] => utility [patent_app_number] => 15/678278 [patent_app_country] => US [patent_app_date] => 2017-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5261 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15678278 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/678278
Systems and methods for efficiently moving data within a filesystem Aug 15, 2017 Issued
Array ( [id] => 14061513 [patent_doc_number] => 10235049 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-03-19 [patent_title] => Device and method to manage access method for memory pages [patent_app_type] => utility [patent_app_number] => 15/678226 [patent_app_country] => US [patent_app_date] => 2017-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 27 [patent_no_of_words] => 11950 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 210 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15678226 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/678226
Device and method to manage access method for memory pages Aug 15, 2017 Issued
Array ( [id] => 13737963 [patent_doc_number] => 20180373450 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-12-27 [patent_title] => GEOMETRY-AWARE COMMAND SCHEDULING [patent_app_type] => utility [patent_app_number] => 15/677941 [patent_app_country] => US [patent_app_date] => 2017-08-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8575 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15677941 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/677941
Geometry-aware command scheduling Aug 14, 2017 Issued
Array ( [id] => 14642505 [patent_doc_number] => 10365997 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-07-30 [patent_title] => Optimizing DRAM memory based on read-to-write ratio of memory access latency [patent_app_type] => utility [patent_app_number] => 15/677654 [patent_app_country] => US [patent_app_date] => 2017-08-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4296 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 223 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15677654 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/677654
Optimizing DRAM memory based on read-to-write ratio of memory access latency Aug 14, 2017 Issued
Array ( [id] => 12060654 [patent_doc_number] => 20170336998 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-11-23 [patent_title] => 'METHOD AND SYSTEM FOR SHARING STORAGE RESOURCE' [patent_app_type] => utility [patent_app_number] => 15/675226 [patent_app_country] => US [patent_app_date] => 2017-08-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 11513 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15675226 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/675226
Method and system for pooling, partitioning, and sharing network storage resources Aug 10, 2017 Issued
Array ( [id] => 15197589 [patent_doc_number] => 10496286 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-12-03 [patent_title] => Apparatuses and methods for parallel writing to multiple memory device structures [patent_app_type] => utility [patent_app_number] => 15/669538 [patent_app_country] => US [patent_app_date] => 2017-08-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 11564 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15669538 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/669538
Apparatuses and methods for parallel writing to multiple memory device structures Aug 3, 2017 Issued
Array ( [id] => 14703991 [patent_doc_number] => 10379740 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-08-13 [patent_title] => Using mirror indicators to indicate whether to mirror tracks in a data set in a primary volume mirrored to a secondary volume [patent_app_type] => utility [patent_app_number] => 15/641041 [patent_app_country] => US [patent_app_date] => 2017-07-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 12 [patent_no_of_words] => 6352 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 261 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15641041 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/641041
Using mirror indicators to indicate whether to mirror tracks in a data set in a primary volume mirrored to a secondary volume Jul 2, 2017 Issued
Array ( [id] => 11996264 [patent_doc_number] => 20170300419 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-10-19 [patent_title] => 'MEMORY ACCESS METHOD, STORAGE-CLASS MEMORY, AND COMPUTER SYSTEM' [patent_app_type] => utility [patent_app_number] => 15/638582 [patent_app_country] => US [patent_app_date] => 2017-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 10403 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15638582 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/638582
Memory access method, storage-class memory, and computer system Jun 29, 2017 Issued
Array ( [id] => 13281671 [patent_doc_number] => 10152420 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-12-11 [patent_title] => Multi-way set associative cache and processing method thereof [patent_app_type] => utility [patent_app_number] => 15/637805 [patent_app_country] => US [patent_app_date] => 2017-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 9650 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 200 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15637805 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/637805
Multi-way set associative cache and processing method thereof Jun 28, 2017 Issued
Array ( [id] => 14426773 [patent_doc_number] => 10318190 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-06-11 [patent_title] => Using mirror indicators to determine whether to mirror tracks in a data set in a primary volume mirrored to a secondary volume [patent_app_type] => utility [patent_app_number] => 15/635093 [patent_app_country] => US [patent_app_date] => 2017-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 12 [patent_no_of_words] => 6349 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 207 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15635093 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/635093
Using mirror indicators to determine whether to mirror tracks in a data set in a primary volume mirrored to a secondary volume Jun 26, 2017 Issued
Array ( [id] => 15758007 [patent_doc_number] => 10621117 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-04-14 [patent_title] => Controlling memory devices using a shared channel [patent_app_type] => utility [patent_app_number] => 15/623514 [patent_app_country] => US [patent_app_date] => 2017-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 4658 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 229 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15623514 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/623514
Controlling memory devices using a shared channel Jun 14, 2017 Issued
Array ( [id] => 13706631 [patent_doc_number] => 20170364270 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-12-21 [patent_title] => METHOD AND SYSTEM FOR MANAGING MEMORY IN STORAGE DEVICE [patent_app_type] => utility [patent_app_number] => 15/623442 [patent_app_country] => US [patent_app_date] => 2017-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7907 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15623442 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/623442
Method and system for allocating and managing storage in a raid storage system Jun 14, 2017 Issued
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