Search

Than Vinh Nguyen

Examiner (ID: 3446, Phone: (571)272-4198 , Office: P/2138 )

Most Active Art Unit
2138
Art Unit(s)
2188, 2138, 2187, 2787, 2759, 2309, 2751
Total Applications
1861
Issued Applications
1652
Pending Applications
79
Abandoned Applications
148

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 11326872 [patent_doc_number] => 20160357484 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-12-08 [patent_title] => 'Increasing the Available Flash Memory of a Microcontroller' [patent_app_type] => utility [patent_app_number] => 15/241202 [patent_app_country] => US [patent_app_date] => 2016-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6464 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15241202 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/241202
Increasing the available flash memory of a microcontroller Aug 18, 2016 Issued
Array ( [id] => 12101882 [patent_doc_number] => 09858980 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-01-02 [patent_title] => 'Memory device refresh commands on the fly' [patent_app_type] => utility [patent_app_number] => 15/213235 [patent_app_country] => US [patent_app_date] => 2016-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6147 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 211 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15213235 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/213235
Memory device refresh commands on the fly Jul 17, 2016 Issued
Array ( [id] => 15373139 [patent_doc_number] => 10528287 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-01-07 [patent_title] => Memory, memory controller, storage apparatus, information processing system, and control method for tracking erase count and rewrite cycles of memory pages [patent_app_type] => utility [patent_app_number] => 15/761590 [patent_app_country] => US [patent_app_date] => 2016-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 29 [patent_no_of_words] => 15887 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15761590 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/761590
Memory, memory controller, storage apparatus, information processing system, and control method for tracking erase count and rewrite cycles of memory pages Jun 30, 2016 Issued
Array ( [id] => 11473644 [patent_doc_number] => 20170060426 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-03-02 [patent_title] => 'STORAGE DEVICE MANAGING NONVOLATILE MEMORY DIFFERENTLY DEPENDING ON TENDENCY OF INTERRUPTION OF POWER SUPPLY' [patent_app_type] => utility [patent_app_number] => 15/176140 [patent_app_country] => US [patent_app_date] => 2016-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 16445 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15176140 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/176140
Storage device managing nonvolatile memory differently depending on tendency of interruption of power supply Jun 6, 2016 Issued
Array ( [id] => 12550893 [patent_doc_number] => 10013179 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-07-03 [patent_title] => Reading logical groups of data from physical locations in memory using headers [patent_app_type] => utility [patent_app_number] => 15/176074 [patent_app_country] => US [patent_app_date] => 2016-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 13754 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 246 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15176074 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/176074
Reading logical groups of data from physical locations in memory using headers Jun 6, 2016 Issued
Array ( [id] => 11672209 [patent_doc_number] => 20170160931 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-06-08 [patent_title] => 'Writing Logical Groups of Data to Physical Locations in Memory Using Headers' [patent_app_type] => utility [patent_app_number] => 15/176070 [patent_app_country] => US [patent_app_date] => 2016-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 18801 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15176070 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/176070
Writing logical groups of data to physical locations in memory using headers Jun 6, 2016 Issued
Array ( [id] => 11838554 [patent_doc_number] => 20170220274 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-08-03 [patent_title] => 'DATA STORAGE DEVICE AND OPERATING METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 15/175998 [patent_app_country] => US [patent_app_date] => 2016-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6074 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15175998 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/175998
Address mapping table recovery upon power failure Jun 6, 2016 Issued
Array ( [id] => 12331977 [patent_doc_number] => 09946653 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-04-17 [patent_title] => Predictive memory caching [patent_app_type] => utility [patent_app_number] => 15/142054 [patent_app_country] => US [patent_app_date] => 2016-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 7120 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15142054 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/142054
Predictive memory caching Apr 28, 2016 Issued
Array ( [id] => 13974553 [patent_doc_number] => 10216633 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-02-26 [patent_title] => Hardware based coherency between a data processing device and interconnect [patent_app_type] => utility [patent_app_number] => 15/141954 [patent_app_country] => US [patent_app_date] => 2016-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7122 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15141954 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/141954
Hardware based coherency between a data processing device and interconnect Apr 28, 2016 Issued
Array ( [id] => 11042364 [patent_doc_number] => 20160239320 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-08-18 [patent_title] => 'FILE MAPPING AND CONVERTING FOR DYNAMIC DISK PERSONALIZATION FOR MULTIPLE PLATFORMS' [patent_app_type] => utility [patent_app_number] => 15/139574 [patent_app_country] => US [patent_app_date] => 2016-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5560 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15139574 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/139574
File mapping and converting for dynamic disk personalization for multiple platforms Apr 26, 2016 Issued
Array ( [id] => 11752179 [patent_doc_number] => 09710191 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-07-18 [patent_title] => 'Rapid memory buffer write storage system and method' [patent_app_type] => utility [patent_app_number] => 15/098156 [patent_app_country] => US [patent_app_date] => 2016-04-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5062 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15098156 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/098156
Rapid memory buffer write storage system and method Apr 12, 2016 Issued
Array ( [id] => 11982161 [patent_doc_number] => 20170286315 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-10-05 [patent_title] => 'MANAGING TRANSLATION INVALIDATION' [patent_app_type] => utility [patent_app_number] => 15/088302 [patent_app_country] => US [patent_app_date] => 2016-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4676 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15088302 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/088302
Managing translation invalidation Mar 31, 2016 Issued
Array ( [id] => 11903509 [patent_doc_number] => 09772943 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-09-26 [patent_title] => 'Managing synonyms in virtual-address caches' [patent_app_type] => utility [patent_app_number] => 15/088354 [patent_app_country] => US [patent_app_date] => 2016-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 6101 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 225 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15088354 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/088354
Managing synonyms in virtual-address caches Mar 31, 2016 Issued
Array ( [id] => 13083701 [patent_doc_number] => 10061918 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-08-28 [patent_title] => System, apparatus and method for filtering memory access logging in a processor [patent_app_type] => utility [patent_app_number] => 15/088318 [patent_app_country] => US [patent_app_date] => 2016-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 7386 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15088318 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/088318
System, apparatus and method for filtering memory access logging in a processor Mar 31, 2016 Issued
Array ( [id] => 13432341 [patent_doc_number] => 20180267713 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-09-20 [patent_title] => METHOD AND APPARATUS FOR DEFINING STORAGE INFRASTRUCTURE [patent_app_type] => utility [patent_app_number] => 15/761798 [patent_app_country] => US [patent_app_date] => 2016-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9276 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15761798 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/761798
METHOD AND APPARATUS FOR DEFINING STORAGE INFRASTRUCTURE Mar 30, 2016 Abandoned
Array ( [id] => 12966472 [patent_doc_number] => 09875052 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-01-23 [patent_title] => Storage capacity allocation using distributed spare space [patent_app_type] => utility [patent_app_number] => 15/070029 [patent_app_country] => US [patent_app_date] => 2016-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 17 [patent_no_of_words] => 8462 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15070029 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/070029
Storage capacity allocation using distributed spare space Mar 14, 2016 Issued
Array ( [id] => 11965703 [patent_doc_number] => 20170269856 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-09-21 [patent_title] => 'DATA REGISTER COPYING FOR NON-VOLATILE STORAGE ARRAY OPERATIONS' [patent_app_type] => utility [patent_app_number] => 15/071100 [patent_app_country] => US [patent_app_date] => 2016-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 12717 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15071100 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/071100
Data register copying for non-volatile storage array operations Mar 14, 2016 Issued
Array ( [id] => 11889932 [patent_doc_number] => 09760493 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-09-12 [patent_title] => 'System and methods of a CPU-efficient cache replacement algorithm' [patent_app_type] => utility [patent_app_number] => 15/069389 [patent_app_country] => US [patent_app_date] => 2016-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 4473 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15069389 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/069389
System and methods of a CPU-efficient cache replacement algorithm Mar 13, 2016 Issued
Array ( [id] => 11759137 [patent_doc_number] => 20170206006 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-07-20 [patent_title] => 'MEMORY MANAGEMENT METHOD, MEMORY STORAGE DEVICE AND MEMORY CONTROL CIRCUIT UNIT' [patent_app_type] => utility [patent_app_number] => 15/069963 [patent_app_country] => US [patent_app_date] => 2016-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 11309 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15069963 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/069963
Garbage collection while maintaining predetermined writing speed Mar 13, 2016 Issued
Array ( [id] => 12108041 [patent_doc_number] => 09864526 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-01-09 [patent_title] => 'Wear leveling using multiple activity counters' [patent_app_type] => utility [patent_app_number] => 15/069155 [patent_app_country] => US [patent_app_date] => 2016-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 9965 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15069155 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/069155
Wear leveling using multiple activity counters Mar 13, 2016 Issued
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