Search

Than Vinh Nguyen

Examiner (ID: 3446, Phone: (571)272-4198 , Office: P/2138 )

Most Active Art Unit
2138
Art Unit(s)
2188, 2138, 2187, 2787, 2759, 2309, 2751
Total Applications
1861
Issued Applications
1652
Pending Applications
79
Abandoned Applications
148

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 10188886 [patent_doc_number] => 09218306 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-12-22 [patent_title] => 'Memory sharing circuit employing a buffered address and data bus and preventing bus collision' [patent_app_type] => utility [patent_app_number] => 13/912064 [patent_app_country] => US [patent_app_date] => 2013-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 6222 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13912064 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/912064
Memory sharing circuit employing a buffered address and data bus and preventing bus collision Jun 5, 2013 Issued
Array ( [id] => 10956198 [patent_doc_number] => 20140359220 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-12-04 [patent_title] => 'Scatter/Gather Capable System Coherent Cache' [patent_app_type] => utility [patent_app_number] => 14/122256 [patent_app_country] => US [patent_app_date] => 2013-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5411 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14122256 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/122256
Scatter/gather capable system coherent cache May 30, 2013 Issued
Array ( [id] => 13083251 [patent_doc_number] => 10061692 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-08-28 [patent_title] => Method and system for automated storage provisioning [patent_app_type] => utility [patent_app_number] => 13/891415 [patent_app_country] => US [patent_app_date] => 2013-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 4733 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 427 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13891415 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/891415
Method and system for automated storage provisioning May 9, 2013 Issued
Array ( [id] => 10021355 [patent_doc_number] => 09063842 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2015-06-23 [patent_title] => 'Technique for integrating VTL tape pools with MTree quotas' [patent_app_type] => utility [patent_app_number] => 13/891789 [patent_app_country] => US [patent_app_date] => 2013-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 12927 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13891789 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/891789
Technique for integrating VTL tape pools with MTree quotas May 9, 2013 Issued
Array ( [id] => 9150477 [patent_doc_number] => 20130305000 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-11-14 [patent_title] => 'SIGNAL PROCESSING CIRCUIT' [patent_app_type] => utility [patent_app_number] => 13/891544 [patent_app_country] => US [patent_app_date] => 2013-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4977 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13891544 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/891544
SIGNAL PROCESSING CIRCUIT May 9, 2013 Abandoned
Array ( [id] => 10072242 [patent_doc_number] => 09110599 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2015-08-18 [patent_title] => 'Thin provisioning of VTL tape pools with MTree logical quotas' [patent_app_type] => utility [patent_app_number] => 13/891808 [patent_app_country] => US [patent_app_date] => 2013-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 18185 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13891808 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/891808
Thin provisioning of VTL tape pools with MTree logical quotas May 9, 2013 Issued
Array ( [id] => 10934560 [patent_doc_number] => 20140337581 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-11-13 [patent_title] => 'POINTER CHASING PREDICTION' [patent_app_type] => utility [patent_app_number] => 13/890716 [patent_app_country] => US [patent_app_date] => 2013-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 7175 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13890716 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/890716
Pointer chasing prediction May 8, 2013 Issued
Array ( [id] => 9947501 [patent_doc_number] => 08996829 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-03-31 [patent_title] => 'Consistency without ordering dependency' [patent_app_type] => utility [patent_app_number] => 13/872896 [patent_app_country] => US [patent_app_date] => 2013-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 8772 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13872896 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/872896
Consistency without ordering dependency Apr 28, 2013 Issued
Array ( [id] => 9017336 [patent_doc_number] => 20130232300 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-09-05 [patent_title] => 'SYSTEM FOR MAINTAINING COHERENCY DURING OFFLINE CHANGES TO STORAGE MEDIA' [patent_app_type] => utility [patent_app_number] => 13/858533 [patent_app_country] => US [patent_app_date] => 2013-04-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4221 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13858533 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/858533
SYSTEM FOR MAINTAINING COHERENCY DURING OFFLINE CHANGES TO STORAGE MEDIA Apr 7, 2013 Abandoned
Array ( [id] => 9006087 [patent_doc_number] => 20130227212 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-08-29 [patent_title] => 'REFRESH REQUEST QUEUING CIRCUITRY' [patent_app_type] => utility [patent_app_number] => 13/857627 [patent_app_country] => US [patent_app_date] => 2013-04-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 6410 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13857627 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/857627
Refresh request queuing circuitry Apr 4, 2013 Issued
Array ( [id] => 11523332 [patent_doc_number] => 09606730 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-03-28 [patent_title] => 'System and method including three dimensional nonvolatile memory device and random access memory' [patent_app_type] => utility [patent_app_number] => 13/799203 [patent_app_country] => US [patent_app_date] => 2013-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 37 [patent_figures_cnt] => 37 [patent_no_of_words] => 16076 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13799203 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/799203
System and method including three dimensional nonvolatile memory device and random access memory Mar 12, 2013 Issued
Array ( [id] => 10596356 [patent_doc_number] => 09317445 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-04-19 [patent_title] => 'Rapid memory buffer write storage system and method' [patent_app_type] => utility [patent_app_number] => 13/764602 [patent_app_country] => US [patent_app_date] => 2013-02-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5042 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13764602 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/764602
Rapid memory buffer write storage system and method Feb 10, 2013 Issued
Array ( [id] => 10471013 [patent_doc_number] => 20150356029 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-12-10 [patent_title] => 'HANDLING MEMORY ACCESS OPERATIONS IN A DATA PROCESSING APPARATUS' [patent_app_type] => utility [patent_app_number] => 14/762976 [patent_app_country] => US [patent_app_date] => 2013-02-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 11688 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14762976 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/762976
Handling memory access protection and address translation in a data processing apparatus Feb 4, 2013 Issued
Array ( [id] => 10860657 [patent_doc_number] => 08886873 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-11-11 [patent_title] => 'Managing memory data recovery upon power loss' [patent_app_type] => utility [patent_app_number] => 13/748199 [patent_app_country] => US [patent_app_date] => 2013-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5185 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13748199 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/748199
Managing memory data recovery upon power loss Jan 22, 2013 Issued
Array ( [id] => 9571572 [patent_doc_number] => 20140189285 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-07-03 [patent_title] => 'Apparatus and Method For Tracking TLB Flushes On A Per Thread Basis' [patent_app_type] => utility [patent_app_number] => 13/730906 [patent_app_country] => US [patent_app_date] => 2012-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3989 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13730906 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/730906
Apparatus and method for tracking TLB flushes on a per thread basis Dec 28, 2012 Issued
Array ( [id] => 9571527 [patent_doc_number] => 20140189240 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-07-03 [patent_title] => 'Apparatus and Method For Reduced Core Entry Into A Power State Having A Powered Down Core Cache' [patent_app_type] => utility [patent_app_number] => 13/730915 [patent_app_country] => US [patent_app_date] => 2012-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5123 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13730915 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/730915
Apparatus and method for reduced core entry into a power state having a powered down core cache Dec 28, 2012 Issued
Array ( [id] => 9571481 [patent_doc_number] => 20140189194 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-07-03 [patent_title] => 'LOW OVERHEAD PAGED MEMORY RUNTIME PROTECTION' [patent_app_type] => utility [patent_app_number] => 13/730920 [patent_app_country] => US [patent_app_date] => 2012-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5415 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13730920 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/730920
Low overhead paged memory runtime protection Dec 28, 2012 Issued
Array ( [id] => 10040976 [patent_doc_number] => 09081682 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-07-14 [patent_title] => 'Virtual machine installation image caching' [patent_app_type] => utility [patent_app_number] => 13/725304 [patent_app_country] => US [patent_app_date] => 2012-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 5073 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13725304 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/725304
Virtual machine installation image caching Dec 20, 2012 Issued
Array ( [id] => 9980401 [patent_doc_number] => 09026731 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-05-05 [patent_title] => 'Memory scheduling for RAM caches based on tag caching' [patent_app_type] => utility [patent_app_number] => 13/725024 [patent_app_country] => US [patent_app_date] => 2012-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 5759 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13725024 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/725024
Memory scheduling for RAM caches based on tag caching Dec 20, 2012 Issued
Array ( [id] => 10507653 [patent_doc_number] => 09235528 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-01-12 [patent_title] => 'Write endurance management techniques in the logic layer of a stacked memory' [patent_app_type] => utility [patent_app_number] => 13/725305 [patent_app_country] => US [patent_app_date] => 2012-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4526 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13725305 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/725305
Write endurance management techniques in the logic layer of a stacked memory Dec 20, 2012 Issued
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