Search

Than Vinh Nguyen

Examiner (ID: 3446, Phone: (571)272-4198 , Office: P/2138 )

Most Active Art Unit
2138
Art Unit(s)
2188, 2138, 2187, 2787, 2759, 2309, 2751
Total Applications
1861
Issued Applications
1652
Pending Applications
79
Abandoned Applications
148

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 9071021 [patent_doc_number] => 20130262777 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-10-03 [patent_title] => 'DATA CACHE BLOCK DEALLOCATE REQUESTS' [patent_app_type] => utility [patent_app_number] => 13/433022 [patent_app_country] => US [patent_app_date] => 2012-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 8152 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13433022 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/433022
Data cache block deallocate requests Mar 27, 2012 Issued
Array ( [id] => 9416809 [patent_doc_number] => 08700861 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-04-15 [patent_title] => 'Managing a dynamic list of entries for cache page cleaning' [patent_app_type] => utility [patent_app_number] => 13/432550 [patent_app_country] => US [patent_app_date] => 2012-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 12 [patent_no_of_words] => 5046 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13432550 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/432550
Managing a dynamic list of entries for cache page cleaning Mar 27, 2012 Issued
Array ( [id] => 9070986 [patent_doc_number] => 20130262742 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-10-03 [patent_title] => 'METHOD AND APPARATUS FOR MANAGING BUFFER CACHE TO PERFORM PAGE REPLACEMENT BY USING REFERENCE TIME INFORMATION REGARDING TIME AT WHICH PAGE IS REFERRED TO' [patent_app_type] => utility [patent_app_number] => 13/433056 [patent_app_country] => US [patent_app_date] => 2012-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6738 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13433056 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/433056
Method and apparatus for managing buffer cache to perform page replacement by using reference time information regarding time at which page is referred to Mar 27, 2012 Issued
Array ( [id] => 8810270 [patent_doc_number] => 08447937 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-05-21 [patent_title] => 'Data migrating method taking end time into consideration' [patent_app_type] => utility [patent_app_number] => 13/426767 [patent_app_country] => US [patent_app_date] => 2012-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 23 [patent_no_of_words] => 13105 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 29 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13426767 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/426767
Data migrating method taking end time into consideration Mar 21, 2012 Issued
Array ( [id] => 8787004 [patent_doc_number] => 08433858 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-04-30 [patent_title] => 'Multi-interface and multi-bus structured solid-state storage subsystem' [patent_app_type] => utility [patent_app_number] => 13/425303 [patent_app_country] => US [patent_app_date] => 2012-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5692 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 250 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13425303 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/425303
Multi-interface and multi-bus structured solid-state storage subsystem Mar 19, 2012 Issued
Array ( [id] => 9044071 [patent_doc_number] => 20130246709 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-09-19 [patent_title] => 'TRANSLATION ADDRESS CACHE FOR A MICROPROCESSOR' [patent_app_type] => utility [patent_app_number] => 13/419323 [patent_app_country] => US [patent_app_date] => 2012-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5025 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13419323 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/419323
Translation address cache for a microprocessor Mar 12, 2012 Issued
Array ( [id] => 9348065 [patent_doc_number] => 08667228 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-03-04 [patent_title] => 'Memory system and method for controlling memory system' [patent_app_type] => utility [patent_app_number] => 13/418432 [patent_app_country] => US [patent_app_date] => 2012-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6335 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 240 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13418432 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/418432
Memory system and method for controlling memory system Mar 12, 2012 Issued
Array ( [id] => 8279966 [patent_doc_number] => 20120173838 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-07-05 [patent_title] => 'DATA STORAGE SYSTEM AND METHOD' [patent_app_type] => utility [patent_app_number] => 13/415601 [patent_app_country] => US [patent_app_date] => 2012-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6064 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13415601 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/415601
Selection of storage containers for thin-partitioned data storage based on criteria Mar 7, 2012 Issued
Array ( [id] => 9257723 [patent_doc_number] => 08621163 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-12-31 [patent_title] => 'Management apparatus for improved database registration and update' [patent_app_type] => utility [patent_app_number] => 13/411763 [patent_app_country] => US [patent_app_date] => 2012-03-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 5952 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 198 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13411763 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/411763
Management apparatus for improved database registration and update Mar 4, 2012 Issued
Array ( [id] => 8229935 [patent_doc_number] => 20120144142 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-06-07 [patent_title] => 'SERIAL ADVANCED TECHNOLOGY ATTACHMENT WRITE PROTECTION: MASS STORAGE DATA PROTECTION DEVICE' [patent_app_type] => utility [patent_app_number] => 13/372924 [patent_app_country] => US [patent_app_date] => 2012-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 13137 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13372924 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/372924
Serial advanced technology attachment write protection: mass storage data protection device Feb 13, 2012 Issued
Array ( [id] => 9585742 [patent_doc_number] => 08775752 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-07-08 [patent_title] => 'Virtual memory management apparatus and memory management apparatus' [patent_app_type] => utility [patent_app_number] => 13/371541 [patent_app_country] => US [patent_app_date] => 2012-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5709 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13371541 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/371541
Virtual memory management apparatus and memory management apparatus Feb 12, 2012 Issued
Array ( [id] => 8229895 [patent_doc_number] => 20120144101 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-06-07 [patent_title] => 'PROGRAMMING MEMORY CELLS WITH ADDITIONAL DATA FOR INCREASED THRESHOLD VOLTAGE RESOLUTION' [patent_app_type] => utility [patent_app_number] => 13/369645 [patent_app_country] => US [patent_app_date] => 2012-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3886 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13369645 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/369645
PROGRAMMING MEMORY CELLS WITH ADDITIONAL DATA FOR INCREASED THRESHOLD VOLTAGE RESOLUTION Feb 8, 2012 Abandoned
Array ( [id] => 10563253 [patent_doc_number] => 09286934 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-03-15 [patent_title] => 'Data duplication in tape drives' [patent_app_type] => utility [patent_app_number] => 14/364486 [patent_app_country] => US [patent_app_date] => 2012-02-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 3352 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14364486 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/364486
Data duplication in tape drives Feb 5, 2012 Issued
Array ( [id] => 8194691 [patent_doc_number] => 20120120310 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-05-17 [patent_title] => 'Programmable Signal Processing Circuit And Method of Interleaving' [patent_app_type] => utility [patent_app_number] => 13/357339 [patent_app_country] => US [patent_app_date] => 2012-01-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5761 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0120/20120120310.pdf [firstpage_image] =>[orig_patent_app_number] => 13357339 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/357339
Programmable signal processing circuit and method of interleaving Jan 23, 2012 Issued
Array ( [id] => 11550326 [patent_doc_number] => 09619174 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-04-11 [patent_title] => 'Write mechanism for storage class memory' [patent_app_type] => utility [patent_app_number] => 13/992809 [patent_app_country] => US [patent_app_date] => 2011-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 2751 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13992809 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/992809
Write mechanism for storage class memory Dec 29, 2011 Issued
Array ( [id] => 9386112 [patent_doc_number] => 20140089595 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-03-27 [patent_title] => 'UTILITY AND LIFETIME BASED CACHE REPLACEMENT POLICY' [patent_app_type] => utility [patent_app_number] => 13/992240 [patent_app_country] => US [patent_app_date] => 2011-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 9322 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13992240 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/992240
Utility and lifetime based cache replacement policy Dec 22, 2011 Issued
Array ( [id] => 9056772 [patent_doc_number] => 20130254486 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-09-26 [patent_title] => 'SPECULATIVE CACHE MODIFICATION' [patent_app_type] => utility [patent_app_number] => 13/992354 [patent_app_country] => US [patent_app_date] => 2011-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 10253 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13992354 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/992354
Speculative cache modification Dec 21, 2011 Issued
Array ( [id] => 9486435 [patent_doc_number] => 08732397 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-05-20 [patent_title] => 'Memory system including first and second caches and controlling readout of data therefrom' [patent_app_type] => utility [patent_app_number] => 13/326929 [patent_app_country] => US [patent_app_date] => 2011-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 18 [patent_no_of_words] => 11218 [patent_no_of_claims] => 46 [patent_no_of_ind_claims] => 14 [patent_words_short_claim] => 228 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13326929 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/326929
Memory system including first and second caches and controlling readout of data therefrom Dec 14, 2011 Issued
Array ( [id] => 8886449 [patent_doc_number] => 20130159633 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-06-20 [patent_title] => 'QOS MANAGEMENT IN THE L2 CACHE' [patent_app_type] => utility [patent_app_number] => 13/326690 [patent_app_country] => US [patent_app_date] => 2011-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7805 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13326690 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/326690
QoS management in the L2 cache Dec 14, 2011 Issued
Array ( [id] => 9486435 [patent_doc_number] => 08732397 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-05-20 [patent_title] => 'Memory system including first and second caches and controlling readout of data therefrom' [patent_app_type] => utility [patent_app_number] => 13/326929 [patent_app_country] => US [patent_app_date] => 2011-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 18 [patent_no_of_words] => 11218 [patent_no_of_claims] => 46 [patent_no_of_ind_claims] => 14 [patent_words_short_claim] => 228 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13326929 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/326929
Memory system including first and second caches and controlling readout of data therefrom Dec 14, 2011 Issued
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