Search

Than Vinh Nguyen

Examiner (ID: 3446, Phone: (571)272-4198 , Office: P/2138 )

Most Active Art Unit
2138
Art Unit(s)
2188, 2138, 2187, 2787, 2759, 2309, 2751
Total Applications
1861
Issued Applications
1652
Pending Applications
79
Abandoned Applications
148

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 987711 [patent_doc_number] => 06925537 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-08-02 [patent_title] => 'Multiprocessor cache coherence system and method in which processor nodes and input/output nodes are equal participants' [patent_app_type] => utility [patent_app_number] => 10/698130 [patent_app_country] => US [patent_app_date] => 2003-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 30 [patent_no_of_words] => 19839 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/925/06925537.pdf [firstpage_image] =>[orig_patent_app_number] => 10698130 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/698130
Multiprocessor cache coherence system and method in which processor nodes and input/output nodes are equal participants Oct 30, 2003 Issued
Array ( [id] => 107619 [patent_doc_number] => 07725649 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-05-25 [patent_title] => 'Recording method and recording apparatus using same' [patent_app_type] => utility [patent_app_number] => 10/674477 [patent_app_country] => US [patent_app_date] => 2003-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 4537 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/725/07725649.pdf [firstpage_image] =>[orig_patent_app_number] => 10674477 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/674477
Recording method and recording apparatus using same Sep 30, 2003 Issued
Array ( [id] => 7234029 [patent_doc_number] => 20040073740 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-04-15 [patent_title] => 'System and method for increasing the snoop bandwidth to cache tags in a cache memory sybsystem' [patent_app_type] => new [patent_app_number] => 10/673654 [patent_app_country] => US [patent_app_date] => 2003-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4253 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0073/20040073740.pdf [firstpage_image] =>[orig_patent_app_number] => 10673654 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/673654
Cache memory system allowing concurrent reads and writes to cache lines to increase snoop bandwith Sep 28, 2003 Issued
Array ( [id] => 7030406 [patent_doc_number] => 20050021906 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-01-27 [patent_title] => 'Storage system' [patent_app_type] => utility [patent_app_number] => 10/648291 [patent_app_country] => US [patent_app_date] => 2003-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 8906 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0021/20050021906.pdf [firstpage_image] =>[orig_patent_app_number] => 10648291 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/648291
Storage system including multiple control units for increased reliability during a failure Aug 26, 2003 Issued
Array ( [id] => 7352687 [patent_doc_number] => 20040193803 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-09-30 [patent_title] => 'Cache management method for storage device' [patent_app_type] => new [patent_app_number] => 10/646699 [patent_app_country] => US [patent_app_date] => 2003-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 26 [patent_no_of_words] => 18422 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0193/20040193803.pdf [firstpage_image] =>[orig_patent_app_number] => 10646699 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/646699
Cache management method for storage device Aug 24, 2003 Issued
Array ( [id] => 7404680 [patent_doc_number] => 20040039882 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-02-26 [patent_title] => 'Information processing method and information processing apparatus' [patent_app_type] => new [patent_app_number] => 10/646653 [patent_app_country] => US [patent_app_date] => 2003-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 14365 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0039/20040039882.pdf [firstpage_image] =>[orig_patent_app_number] => 10646653 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/646653
Information processing method and apparatus having data locations accessible by different devices in accordance with different permissions Aug 20, 2003 Issued
Array ( [id] => 7234880 [patent_doc_number] => 20040073846 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-04-15 [patent_title] => 'Memory device, terminal apparatus, and data repair system' [patent_app_type] => new [patent_app_number] => 10/467067 [patent_app_country] => US [patent_app_date] => 2003-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 8505 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 39 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0073/20040073846.pdf [firstpage_image] =>[orig_patent_app_number] => 10467067 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/467067
Memory device, terminal apparatus, and data repair system Aug 18, 2003 Abandoned
Array ( [id] => 7036169 [patent_doc_number] => 20050033905 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-02-10 [patent_title] => 'Split T-chain memory command and address bus topology' [patent_app_type] => utility [patent_app_number] => 10/638069 [patent_app_country] => US [patent_app_date] => 2003-08-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2169 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0033/20050033905.pdf [firstpage_image] =>[orig_patent_app_number] => 10638069 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/638069
Memory system and method to reduce reflection and signal degradation Aug 7, 2003 Issued
Array ( [id] => 7360615 [patent_doc_number] => 20040049638 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-03-11 [patent_title] => 'Method for data retention in a data cache and data storage system' [patent_app_type] => new [patent_app_number] => 10/635275 [patent_app_country] => US [patent_app_date] => 2003-08-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3225 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0049/20040049638.pdf [firstpage_image] =>[orig_patent_app_number] => 10635275 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/635275
Method for data retention in a data cache and data storage system Aug 5, 2003 Issued
Array ( [id] => 7214636 [patent_doc_number] => 20040088509 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-05-06 [patent_title] => 'Microprocessor circuit for data carriers and method for organizing access to data stored in a memory' [patent_app_type] => new [patent_app_number] => 10/635599 [patent_app_country] => US [patent_app_date] => 2003-08-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5898 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0088/20040088509.pdf [firstpage_image] =>[orig_patent_app_number] => 10635599 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/635599
Microprocessor circuit for data carriers and method for organizing access to data stored in a memory Aug 5, 2003 Issued
Array ( [id] => 7374729 [patent_doc_number] => 20040027882 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-02-12 [patent_title] => 'Semiconductor memory device and control method therefor' [patent_app_type] => new [patent_app_number] => 10/634758 [patent_app_country] => US [patent_app_date] => 2003-08-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 8376 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0027/20040027882.pdf [firstpage_image] =>[orig_patent_app_number] => 10634758 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/634758
Memory device and method for arbitrating internal and external access Aug 5, 2003 Issued
Array ( [id] => 680064 [patent_doc_number] => 07089398 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-08-08 [patent_title] => 'Address translation using a page size tag' [patent_app_type] => utility [patent_app_number] => 10/632131 [patent_app_country] => US [patent_app_date] => 2003-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 6027 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/089/07089398.pdf [firstpage_image] =>[orig_patent_app_number] => 10632131 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/632131
Address translation using a page size tag Jul 30, 2003 Issued
Array ( [id] => 675941 [patent_doc_number] => 07093066 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-08-15 [patent_title] => 'Method for bus capacitance reduction' [patent_app_type] => utility [patent_app_number] => 10/615326 [patent_app_country] => US [patent_app_date] => 2003-07-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 4085 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/093/07093066.pdf [firstpage_image] =>[orig_patent_app_number] => 10615326 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/615326
Method for bus capacitance reduction Jul 6, 2003 Issued
Array ( [id] => 411403 [patent_doc_number] => 07287136 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-10-23 [patent_title] => 'Cache device, and method and computer program for controlling cached data' [patent_app_type] => utility [patent_app_number] => 10/520427 [patent_app_country] => US [patent_app_date] => 2003-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 14981 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/287/07287136.pdf [firstpage_image] =>[orig_patent_app_number] => 10520427 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/520427
Cache device, and method and computer program for controlling cached data Jun 23, 2003 Issued
Array ( [id] => 641136 [patent_doc_number] => 07127576 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-10-24 [patent_title] => 'Method and system for data duplication' [patent_app_type] => utility [patent_app_number] => 10/444155 [patent_app_country] => US [patent_app_date] => 2003-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 4644 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 222 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/127/07127576.pdf [firstpage_image] =>[orig_patent_app_number] => 10444155 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/444155
Method and system for data duplication May 20, 2003 Issued
Array ( [id] => 6927472 [patent_doc_number] => 20050240729 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-10-27 [patent_title] => 'Access to a wide memory' [patent_app_type] => utility [patent_app_number] => 10/515452 [patent_app_country] => US [patent_app_date] => 2003-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 7216 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0240/20050240729.pdf [firstpage_image] =>[orig_patent_app_number] => 10515452 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/515452
Access to a wide memory May 6, 2003 Issued
Array ( [id] => 5739864 [patent_doc_number] => 20060010255 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-01-12 [patent_title] => 'Address generation unit for a processor' [patent_app_type] => utility [patent_app_number] => 10/515462 [patent_app_country] => US [patent_app_date] => 2003-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 7954 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0010/20060010255.pdf [firstpage_image] =>[orig_patent_app_number] => 10515462 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/515462
Address generation unit for a processor May 6, 2003 Issued
Array ( [id] => 721677 [patent_doc_number] => 07055006 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-05-30 [patent_title] => 'System and method for blocking cache use during debugging' [patent_app_type] => utility [patent_app_number] => 10/426755 [patent_app_country] => US [patent_app_date] => 2003-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4947 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/055/07055006.pdf [firstpage_image] =>[orig_patent_app_number] => 10426755 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/426755
System and method for blocking cache use during debugging Apr 29, 2003 Issued
Array ( [id] => 721701 [patent_doc_number] => 07055016 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-05-30 [patent_title] => 'Computer system including a memory controller configured to perform pre-fetch operations' [patent_app_type] => utility [patent_app_number] => 10/426565 [patent_app_country] => US [patent_app_date] => 2003-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 6123 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/055/07055016.pdf [firstpage_image] =>[orig_patent_app_number] => 10426565 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/426565
Computer system including a memory controller configured to perform pre-fetch operations Apr 29, 2003 Issued
Array ( [id] => 7384689 [patent_doc_number] => 20040221107 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-11-04 [patent_title] => 'Multiprocessor write-into-cache system incorporating efficient access to a plurality of gatewords' [patent_app_type] => new [patent_app_number] => 10/426409 [patent_app_country] => US [patent_app_date] => 2003-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 7483 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 428 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0221/20040221107.pdf [firstpage_image] =>[orig_patent_app_number] => 10426409 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/426409
Multiprocessor write-into-cache system incorporating efficient access to a plurality of gatewords Apr 29, 2003 Issued
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