Than Vinh Nguyen

Array ( [id] => 1243105 [patent_doc_number] => 06684296 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-01-27 [patent_title] => 'Source controlled cache allocation' [patent_app_type] => B2 [patent_app_number] => 10/394132 [patent_app_country] => US [patent_app_date] => 2003-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 12938 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/684/06684296.pdf [firstpage_image] =>[orig_patent_app_number] => 10394132 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6741646 [patent_doc_number] => 20030159015 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-08-21 [patent_title] => 'INFORMATION STORAGE AND RETRIEVAL SYSTEM' [patent_app_type] => new [patent_app_number] => 10/390815 [patent_app_country] => US [patent_app_date] => 2003-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4714 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0159/20030159015.pdf [firstpage_image] =>[orig_patent_app_number] => 10390815 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6622374 [patent_doc_number] => 20030210585 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-11-13 [patent_title] => 'Non-volatile memory device' [patent_app_type] => new [patent_app_number] => 10/390556 [patent_app_country] => US [patent_app_date] => 2003-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4155 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 26 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0210/20030210585.pdf [firstpage_image] =>[orig_patent_app_number] => 10390556 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7603636 [patent_doc_number] => 07117303 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-10-03 [patent_title] => 'Efficient, robust file handle invalidation' [patent_app_type] => utility [patent_app_number] => 10/389451 [patent_app_country] => US [patent_app_date] => 2003-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 10388 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 13 [patent_words_short_claim] => 51 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/117/07117303.pdf [firstpage_image] =>[orig_patent_app_number] => 10389451 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 765249 [patent_doc_number] => 07017028 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-03-21 [patent_title] => 'Apparatus and method for updating pointers for indirect and parallel register access' [patent_app_type] => utility [patent_app_number] => 10/389212 [patent_app_country] => US [patent_app_date] => 2003-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2673 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/017/07017028.pdf [firstpage_image] =>[orig_patent_app_number] => 10389212 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1001722 [patent_doc_number] => 06912640 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-06-28 [patent_title] => 'Method to partition large code across multiple e-caches' [patent_app_type] => utility [patent_app_number] => 10/389270 [patent_app_country] => US [patent_app_date] => 2003-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4854 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/912/06912640.pdf [firstpage_image] =>[orig_patent_app_number] => 10389270 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6712397 [patent_doc_number] => 20030172146 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-09-11 [patent_title] => 'Aggregation of available storage capacity derived from storage devices attached to computers, and allocation of same as logical device' [patent_app_type] => new [patent_app_number] => 10/389133 [patent_app_country] => US [patent_app_date] => 2003-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6576 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0172/20030172146.pdf [firstpage_image] =>[orig_patent_app_number] => 10389133 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7672143 [patent_doc_number] => 20040181636 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-09-16 [patent_title] => 'Token based cache-coherence protocol' [patent_app_type] => new [patent_app_number] => 10/389861 [patent_app_country] => US [patent_app_date] => 2003-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6669 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0181/20040181636.pdf [firstpage_image] =>[orig_patent_app_number] => 10389861 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6665363 [patent_doc_number] => 20030204690 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-10-30 [patent_title] => 'Data back up method and its programs' [patent_app_type] => new [patent_app_number] => 10/367767 [patent_app_country] => US [patent_app_date] => 2003-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4876 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0204/20030204690.pdf [firstpage_image] =>[orig_patent_app_number] => 10367767 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7440269 [patent_doc_number] => 20040162949 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-08-19 [patent_title] => 'Optimized high bandwidth cache coherence mechanism' [patent_app_type] => new [patent_app_number] => 10/368090 [patent_app_country] => US [patent_app_date] => 2003-02-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 10431 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 37 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0162/20040162949.pdf [firstpage_image] =>[orig_patent_app_number] => 10368090 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6741643 [patent_doc_number] => 20030159012 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-08-21 [patent_title] => 'Back-up system' [patent_app_type] => new [patent_app_number] => 10/368203 [patent_app_country] => US [patent_app_date] => 2003-02-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5843 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0159/20030159012.pdf [firstpage_image] =>[orig_patent_app_number] => 10368203 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6670442 [patent_doc_number] => 20030115427 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-06-19 [patent_title] => 'Tri-stating output buffer during initialization of synchronous memory' [patent_app_type] => new [patent_app_number] => 10/352397 [patent_app_country] => US [patent_app_date] => 2003-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3443 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 33 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0115/20030115427.pdf [firstpage_image] =>[orig_patent_app_number] => 10352397 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7109787 [patent_doc_number] => 20050207241 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-09-22 [patent_title] => 'Semiconductor storage method and apparatus for implementing imormation prompt' [patent_app_type] => utility [patent_app_number] => 10/519437 [patent_app_country] => US [patent_app_date] => 2003-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 7186 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0207/20050207241.pdf [firstpage_image] =>[orig_patent_app_number] => 10519437 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6661063 [patent_doc_number] => 20030135707 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-07-17 [patent_title] => 'Semiconductor memory device with fast masking process in burst write mode' [patent_app_type] => new [patent_app_number] => 10/327096 [patent_app_country] => US [patent_app_date] => 2002-12-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 28 [patent_no_of_words] => 9466 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 41 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0135/20030135707.pdf [firstpage_image] =>[orig_patent_app_number] => 10327096 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7476857 [patent_doc_number] => 20040123045 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-06-24 [patent_title] => 'Hierarchical virtual model of a cache hierarchy in a multiprocessor system' [patent_app_type] => new [patent_app_number] => 10/324711 [patent_app_country] => US [patent_app_date] => 2002-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 7709 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0123/20040123045.pdf [firstpage_image] =>[orig_patent_app_number] => 10324711 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7476855 [patent_doc_number] => 20040123043 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-06-24 [patent_title] => 'High performance memory device-state aware chipset prefetcher' [patent_app_type] => new [patent_app_number] => 10/325795 [patent_app_country] => US [patent_app_date] => 2002-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3803 [patent_no_of_claims] => 42 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0123/20040123043.pdf [firstpage_image] =>[orig_patent_app_number] => 10325795 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7603633 [patent_doc_number] => 07117306 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-10-03 [patent_title] => 'Mitigating access penalty of a semiconductor nonvolatile memory' [patent_app_type] => utility [patent_app_number] => 10/324445 [patent_app_country] => US [patent_app_date] => 2002-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 4949 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 29 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/117/07117306.pdf [firstpage_image] =>[orig_patent_app_number] => 10324445 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 989474 [patent_doc_number] => 06922756 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-07-26 [patent_title] => 'Forward state for use in cache coherency in a multiprocessor system' [patent_app_type] => utility [patent_app_number] => 10/325069 [patent_app_country] => US [patent_app_date] => 2002-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5662 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/922/06922756.pdf [firstpage_image] =>[orig_patent_app_number] => 10325069 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7476854 [patent_doc_number] => 20040123042 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-06-24 [patent_title] => 'Memory power management using prefetch buffers' [patent_app_type] => new [patent_app_number] => 10/324512 [patent_app_country] => US [patent_app_date] => 2002-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1924 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0123/20040123042.pdf [firstpage_image] =>[orig_patent_app_number] => 10324512 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 958118 [patent_doc_number] => 06957309 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-10-18 [patent_title] => 'Method and apparatus for re-accessing a FIFO location' [patent_app_type] => utility [patent_app_number] => 10/324308 [patent_app_country] => US [patent_app_date] => 2002-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3390 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/957/06957309.pdf [firstpage_image] =>[orig_patent_app_number] => 10324308 [rel_patent_id] =>[rel_patent_doc_number] =>)