Search

Than Vinh Nguyen

Examiner (ID: 3446, Phone: (571)272-4198 , Office: P/2138 )

Most Active Art Unit
2138
Art Unit(s)
2188, 2138, 2187, 2787, 2759, 2309, 2751
Total Applications
1861
Issued Applications
1652
Pending Applications
79
Abandoned Applications
148

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 6862616 [patent_doc_number] => 20030093624 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-05-15 [patent_title] => 'Symmetric multiprocessor systems with an independent super-coherent cache directory' [patent_app_type] => new [patent_app_number] => 09/978363 [patent_app_country] => US [patent_app_date] => 2001-10-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 12508 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0093/20030093624.pdf [firstpage_image] =>[orig_patent_app_number] => 09978363 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/978363
Symmetric multiprocessor systems with an independent super-coherent cache directory Oct 15, 2001 Issued
Array ( [id] => 1180939 [patent_doc_number] => 06754769 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-06-22 [patent_title] => 'Disk array controller using crossbar switches and method of controlling the same' [patent_app_type] => B2 [patent_app_number] => 09/976060 [patent_app_country] => US [patent_app_date] => 2001-10-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7077 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/754/06754769.pdf [firstpage_image] =>[orig_patent_app_number] => 09976060 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/976060
Disk array controller using crossbar switches and method of controlling the same Oct 14, 2001 Issued
Array ( [id] => 6814971 [patent_doc_number] => 20030074521 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-04-17 [patent_title] => 'Data storage device for fast multiple file write operations' [patent_app_type] => new [patent_app_number] => 09/977467 [patent_app_country] => US [patent_app_date] => 2001-10-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 5565 [patent_no_of_claims] => 42 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0074/20030074521.pdf [firstpage_image] =>[orig_patent_app_number] => 09977467 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/977467
Data storage device for fast multiple file write operations Oct 14, 2001 Issued
Array ( [id] => 6814972 [patent_doc_number] => 20030074522 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-04-17 [patent_title] => 'Data management system, apparatus, and method to use buffered file marks' [patent_app_type] => new [patent_app_number] => 09/977468 [patent_app_country] => US [patent_app_date] => 2001-10-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 4665 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0074/20030074522.pdf [firstpage_image] =>[orig_patent_app_number] => 09977468 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/977468
Data management system, apparatus, and method to use buffered file marks Oct 14, 2001 Abandoned
Array ( [id] => 959960 [patent_doc_number] => 06954824 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-10-11 [patent_title] => 'Method, system, and program for determining a configuration of a logical array including a plurality of storage devices' [patent_app_type] => utility [patent_app_number] => 09/978942 [patent_app_country] => US [patent_app_date] => 2001-10-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5254 [patent_no_of_claims] => 51 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/954/06954824.pdf [firstpage_image] =>[orig_patent_app_number] => 09978942 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/978942
Method, system, and program for determining a configuration of a logical array including a plurality of storage devices Oct 14, 2001 Issued
Array ( [id] => 1229201 [patent_doc_number] => 06701419 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-03-02 [patent_title] => 'Interlaced memory device with random or sequential access' [patent_app_type] => B2 [patent_app_number] => 09/977561 [patent_app_country] => US [patent_app_date] => 2001-10-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 17 [patent_no_of_words] => 5910 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 184 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/701/06701419.pdf [firstpage_image] =>[orig_patent_app_number] => 09977561 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/977561
Interlaced memory device with random or sequential access Oct 14, 2001 Issued
Array ( [id] => 1214421 [patent_doc_number] => 06715055 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-03-30 [patent_title] => 'Apparatus and method for allocating buffer space' [patent_app_type] => B1 [patent_app_number] => 09/981618 [patent_app_country] => US [patent_app_date] => 2001-10-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 8029 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/715/06715055.pdf [firstpage_image] =>[orig_patent_app_number] => 09981618 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/981618
Apparatus and method for allocating buffer space Oct 14, 2001 Issued
Array ( [id] => 1155092 [patent_doc_number] => 06779080 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-08-17 [patent_title] => 'Serial data storage system with automatically adjusted data protection to implement worm media with limited overwrite allowing write appending' [patent_app_type] => B2 [patent_app_number] => 09/978117 [patent_app_country] => US [patent_app_date] => 2001-10-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 6563 [patent_no_of_claims] => 50 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 217 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/779/06779080.pdf [firstpage_image] =>[orig_patent_app_number] => 09978117 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/978117
Serial data storage system with automatically adjusted data protection to implement worm media with limited overwrite allowing write appending Oct 14, 2001 Issued
Array ( [id] => 6814969 [patent_doc_number] => 20030074519 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-04-17 [patent_title] => 'Method and apparatus for scheduling of requests to dynamic random access memory device' [patent_app_type] => new [patent_app_number] => 09/977510 [patent_app_country] => US [patent_app_date] => 2001-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3081 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0074/20030074519.pdf [firstpage_image] =>[orig_patent_app_number] => 09977510 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/977510
Method and apparatus for scheduling of requests to dynamic random access memory device Oct 11, 2001 Issued
Array ( [id] => 6244961 [patent_doc_number] => 20020046205 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-04-18 [patent_title] => 'Method of operating a hierarchical data document system having a duplicate tree structure' [patent_app_type] => new [patent_app_number] => 09/962952 [patent_app_country] => US [patent_app_date] => 2001-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 5646 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0046/20020046205.pdf [firstpage_image] =>[orig_patent_app_number] => 09962952 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/962952
Method of operating a hierarchical data document system having a duplicate tree structure Sep 24, 2001 Issued
Array ( [id] => 6675928 [patent_doc_number] => 20030061531 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-03-27 [patent_title] => 'Reconfiguring memory to reduce boot time' [patent_app_type] => new [patent_app_number] => 09/962906 [patent_app_country] => US [patent_app_date] => 2001-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5908 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 37 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0061/20030061531.pdf [firstpage_image] =>[orig_patent_app_number] => 09962906 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/962906
Reconfiguring memory to reduce boot time Sep 24, 2001 Issued
Array ( [id] => 7618452 [patent_doc_number] => 06944739 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-09-13 [patent_title] => 'Register bank' [patent_app_type] => utility [patent_app_number] => 09/957283 [patent_app_country] => US [patent_app_date] => 2001-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 6770 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/944/06944739.pdf [firstpage_image] =>[orig_patent_app_number] => 09957283 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/957283
Register bank Sep 19, 2001 Issued
Array ( [id] => 1088616 [patent_doc_number] => 06832301 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-12-14 [patent_title] => 'Method for recovering memory' [patent_app_type] => B2 [patent_app_number] => 09/950422 [patent_app_country] => US [patent_app_date] => 2001-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3760 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 190 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/832/06832301.pdf [firstpage_image] =>[orig_patent_app_number] => 09950422 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/950422
Method for recovering memory Sep 10, 2001 Issued
Array ( [id] => 6656251 [patent_doc_number] => 20030009647 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-01-09 [patent_title] => 'Method of selecting registers' [patent_app_type] => new [patent_app_number] => 09/940393 [patent_app_country] => US [patent_app_date] => 2001-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3107 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0009/20030009647.pdf [firstpage_image] =>[orig_patent_app_number] => 09940393 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/940393
Method of selecting registers from a primitive register set Aug 26, 2001 Issued
Array ( [id] => 5803513 [patent_doc_number] => 20020010843 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-01-24 [patent_title] => 'Fiber channel connection storage controller' [patent_app_type] => new [patent_app_number] => 09/933173 [patent_app_country] => US [patent_app_date] => 2001-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 6446 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0010/20020010843.pdf [firstpage_image] =>[orig_patent_app_number] => 09933173 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/933173
Fiber channel connection storage controller Aug 20, 2001 Issued
Array ( [id] => 1179087 [patent_doc_number] => 06757799 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-06-29 [patent_title] => 'Memory device with pipelined address path' [patent_app_type] => B2 [patent_app_number] => 09/920780 [patent_app_country] => US [patent_app_date] => 2001-08-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 4789 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/757/06757799.pdf [firstpage_image] =>[orig_patent_app_number] => 09920780 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/920780
Memory device with pipelined address path Jul 31, 2001 Issued
Array ( [id] => 6899297 [patent_doc_number] => 20010047462 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-11-29 [patent_title] => 'Cascaded removable media data storage system' [patent_app_type] => new [patent_app_number] => 09/919175 [patent_app_country] => US [patent_app_date] => 2001-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 6417 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0047/20010047462.pdf [firstpage_image] =>[orig_patent_app_number] => 09919175 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/919175
Cascaded removable media data storage system Jul 30, 2001 Abandoned
Array ( [id] => 526623 [patent_doc_number] => 07200712 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-04-03 [patent_title] => 'Associative memory system, network device, and network system' [patent_app_type] => utility [patent_app_number] => 10/481712 [patent_app_country] => US [patent_app_date] => 2001-07-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 27 [patent_no_of_words] => 41124 [patent_no_of_claims] => 53 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 286 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/200/07200712.pdf [firstpage_image] =>[orig_patent_app_number] => 10481712 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/481712
Associative memory system, network device, and network system Jul 23, 2001 Issued
Array ( [id] => 1432389 [patent_doc_number] => 06505281 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-01-07 [patent_title] => 'Hard disk drives employing high speed distribution bus' [patent_app_type] => B1 [patent_app_number] => 09/908233 [patent_app_country] => US [patent_app_date] => 2001-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 22 [patent_no_of_words] => 29001 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/505/06505281.pdf [firstpage_image] =>[orig_patent_app_number] => 09908233 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/908233
Hard disk drives employing high speed distribution bus Jul 17, 2001 Issued
Array ( [id] => 1210385 [patent_doc_number] => 06718449 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-04-06 [patent_title] => 'System for data transfer between different clock domains, and for obtaining status of memory device during transfer' [patent_app_type] => B2 [patent_app_number] => 09/901738 [patent_app_country] => US [patent_app_date] => 2001-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 2984 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 13 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/718/06718449.pdf [firstpage_image] =>[orig_patent_app_number] => 09901738 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/901738
System for data transfer between different clock domains, and for obtaining status of memory device during transfer Jul 8, 2001 Issued
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