Than Vinh Nguyen

Array ( [id] => 1432366 [patent_doc_number] => 06505258 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-01-07 [patent_title] => 'Comprehensive interface between bios and device drivers to signal events' [patent_app_type] => B1 [patent_app_number] => 09/515436 [patent_app_country] => US [patent_app_date] => 2000-02-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 8420 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/505/06505258.pdf [firstpage_image] =>[orig_patent_app_number] => 09515436 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1395568 [patent_doc_number] => 06567901 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-05-20 [patent_title] => 'Read around speculative load' [patent_app_type] => B1 [patent_app_number] => 09/514981 [patent_app_country] => US [patent_app_date] => 2000-02-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3483 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/567/06567901.pdf [firstpage_image] =>[orig_patent_app_number] => 09514981 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1524917 [patent_doc_number] => 06415371 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-07-02 [patent_title] => 'Storage system, storage device, storage medium controller, access device, method for protecting data, storage medium and computer data signal' [patent_app_type] => B1 [patent_app_number] => 09/514992 [patent_app_country] => US [patent_app_date] => 2000-02-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 10813 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 12 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/415/06415371.pdf [firstpage_image] =>[orig_patent_app_number] => 09514992 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1425154 [patent_doc_number] => 06535951 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-03-18 [patent_title] => 'Hit result register file used in a CAM' [patent_app_type] => B1 [patent_app_number] => 09/515578 [patent_app_country] => US [patent_app_date] => 2000-02-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 5113 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/535/06535951.pdf [firstpage_image] =>[orig_patent_app_number] => 09515578 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1456771 [patent_doc_number] => 06457107 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-09-24 [patent_title] => 'Method and apparatus for reducing false sharing in a distributed computing environment' [patent_app_type] => B1 [patent_app_number] => 09/514514 [patent_app_country] => US [patent_app_date] => 2000-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 4289 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/457/06457107.pdf [firstpage_image] =>[orig_patent_app_number] => 09514514 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1444067 [patent_doc_number] => 06496899 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-12-17 [patent_title] => 'Disk scheduling system with bounded request reordering' [patent_app_type] => B1 [patent_app_number] => 09/514485 [patent_app_country] => US [patent_app_date] => 2000-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 16 [patent_no_of_words] => 10907 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/496/06496899.pdf [firstpage_image] =>[orig_patent_app_number] => 09514485 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1361345 [patent_doc_number] => 06587928 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-07-01 [patent_title] => 'Scheme for segregating cacheable and non-cacheable by port designation' [patent_app_type] => B1 [patent_app_number] => 09/515069 [patent_app_country] => US [patent_app_date] => 2000-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 3316 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 33 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/587/06587928.pdf [firstpage_image] =>[orig_patent_app_number] => 09515069 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1519660 [patent_doc_number] => 06421767 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-07-16 [patent_title] => 'Method and apparatus for managing a storage system using snapshot copy operations with snap groups' [patent_app_type] => B1 [patent_app_number] => 09/511886 [patent_app_country] => US [patent_app_date] => 2000-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 6641 [patent_no_of_claims] => 39 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/421/06421767.pdf [firstpage_image] =>[orig_patent_app_number] => 09511886 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1418840 [patent_doc_number] => 06546471 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-04-08 [patent_title] => 'Shared memory multiprocessor performing cache coherency' [patent_app_type] => B1 [patent_app_number] => 09/506810 [patent_app_country] => US [patent_app_date] => 2000-02-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 20 [patent_no_of_words] => 11370 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/546/06546471.pdf [firstpage_image] =>[orig_patent_app_number] => 09506810 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1289028 [patent_doc_number] => 06647464 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-11-11 [patent_title] => 'System and method utilizing speculative cache access for improved performance' [patent_app_type] => B2 [patent_app_number] => 09/507546 [patent_app_country] => US [patent_app_date] => 2000-02-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 6422 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/647/06647464.pdf [firstpage_image] =>[orig_patent_app_number] => 09507546 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4399400 [patent_doc_number] => 06295594 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-25 [patent_title] => 'Dynamic memory allocation suitable for stride-based prefetching' [patent_app_type] => 1 [patent_app_number] => 9/506427 [patent_app_country] => US [patent_app_date] => 2000-02-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 8158 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/295/06295594.pdf [firstpage_image] =>[orig_patent_app_number] => 506427 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1462447 [patent_doc_number] => 06427198 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-07-30 [patent_title] => 'Method, system, and program for determining system configuration' [patent_app_type] => B1 [patent_app_number] => 09/504766 [patent_app_country] => US [patent_app_date] => 2000-02-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5266 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/427/06427198.pdf [firstpage_image] =>[orig_patent_app_number] => 09504766 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1521742 [patent_doc_number] => 06502178 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-12-31 [patent_title] => 'Method, system, and program for mapping logical addresses to high performance zones on a storage medium' [patent_app_type] => B1 [patent_app_number] => 09/503279 [patent_app_country] => US [patent_app_date] => 2000-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 3965 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/502/06502178.pdf [firstpage_image] =>[orig_patent_app_number] => 09503279 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1524853 [patent_doc_number] => 06415352 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-07-02 [patent_title] => 'One-chip microcomputer and method of refreshing its data' [patent_app_type] => B1 [patent_app_number] => 09/503516 [patent_app_country] => US [patent_app_date] => 2000-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 13 [patent_no_of_words] => 3919 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/415/06415352.pdf [firstpage_image] =>[orig_patent_app_number] => 09503516 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1592302 [patent_doc_number] => 06360298 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-03-19 [patent_title] => 'Load/store instruction control circuit of microprocessor and load/store instruction control method' [patent_app_type] => B1 [patent_app_number] => 09/502550 [patent_app_country] => US [patent_app_date] => 2000-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 6314 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/360/06360298.pdf [firstpage_image] =>[orig_patent_app_number] => 09502550 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1539127 [patent_doc_number] => 06412040 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-06-25 [patent_title] => 'Method of performing reliable updates in a symmetrically blocked nonvolatile memory having a bifurcated storage architecture' [patent_app_type] => B2 [patent_app_number] => 09/489182 [patent_app_country] => US [patent_app_date] => 2000-01-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 29 [patent_no_of_words] => 14875 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/412/06412040.pdf [firstpage_image] =>[orig_patent_app_number] => 09489182 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1466163 [patent_doc_number] => 06393515 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-21 [patent_title] => 'Multi-stream associative memory architecture for computer telephony' [patent_app_type] => B1 [patent_app_number] => 09/478253 [patent_app_country] => US [patent_app_date] => 2000-01-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 2688 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/393/06393515.pdf [firstpage_image] =>[orig_patent_app_number] => 09478253 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1584734 [patent_doc_number] => 06449684 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-09-10 [patent_title] => 'Data carrying device and systems for use therewith' [patent_app_type] => B1 [patent_app_number] => 09/462026 [patent_app_country] => US [patent_app_date] => 1999-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4262 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/449/06449684.pdf [firstpage_image] =>[orig_patent_app_number] => 09462026 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1481059 [patent_doc_number] => 06389512 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-14 [patent_title] => 'Microprocessor configured to detect updates to instructions outstanding within an instruction processing pipeline and computer system including same' [patent_app_type] => B1 [patent_app_number] => 09/474790 [patent_app_country] => US [patent_app_date] => 1999-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 7258 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/389/06389512.pdf [firstpage_image] =>[orig_patent_app_number] => 09474790 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1431014 [patent_doc_number] => 06507889 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-01-14 [patent_title] => 'Recording medium library device and control method thereof' [patent_app_type] => B1 [patent_app_number] => 09/458380 [patent_app_country] => US [patent_app_date] => 1999-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 18 [patent_no_of_words] => 14649 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 197 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/507/06507889.pdf [firstpage_image] =>[orig_patent_app_number] => 09458380 [rel_patent_id] =>[rel_patent_doc_number] =>)