Than Vinh Nguyen

Array ( [id] => 4208694 [patent_doc_number] => 06154806 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-28 [patent_title] => 'Method for recording digital signals on multiple-layered disks' [patent_app_type] => 1 [patent_app_number] => 9/339816 [patent_app_country] => US [patent_app_date] => 1999-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 3192 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 245 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/154/06154806.pdf [firstpage_image] =>[orig_patent_app_number] => 339816 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4152747 [patent_doc_number] => 06148387 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-14 [patent_title] => 'System and method for securely utilizing basic input and output system (BIOS) services' [patent_app_type] => 1 [patent_app_number] => 9/336889 [patent_app_country] => US [patent_app_date] => 1999-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 22 [patent_no_of_words] => 12554 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/148/06148387.pdf [firstpage_image] =>[orig_patent_app_number] => 336889 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1466655 [patent_doc_number] => 06351788 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-02-26 [patent_title] => 'Data processor and data processing system' [patent_app_type] => B1 [patent_app_number] => 09/297310 [patent_app_country] => US [patent_app_date] => 1999-06-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 6397 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/351/06351788.pdf [firstpage_image] =>[orig_patent_app_number] => 09297310 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4391280 [patent_doc_number] => 06289397 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-11 [patent_title] => 'Disk drive or like peripheral storage device adapted for firmware upgrading, self-testing, etc.' [patent_app_type] => 1 [patent_app_number] => 9/326423 [patent_app_country] => US [patent_app_date] => 1999-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 6650 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 197 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/289/06289397.pdf [firstpage_image] =>[orig_patent_app_number] => 326423 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4292235 [patent_doc_number] => 06247099 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-12 [patent_title] => 'System and method for maintaining cache coherency and data synchronization in a computer system having multiple active controllers' [patent_app_type] => 1 [patent_app_number] => 9/325033 [patent_app_country] => US [patent_app_date] => 1999-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 30 [patent_no_of_words] => 11366 [patent_no_of_claims] => 41 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/247/06247099.pdf [firstpage_image] =>[orig_patent_app_number] => 325033 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1459999 [patent_doc_number] => 06463503 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-10-08 [patent_title] => 'Method and system for increasing concurrency during staging and destaging in a log structured array' [patent_app_type] => B1 [patent_app_number] => 09/311209 [patent_app_country] => US [patent_app_date] => 1999-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4459 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/463/06463503.pdf [firstpage_image] =>[orig_patent_app_number] => 09311209 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1490105 [patent_doc_number] => 06366984 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-02 [patent_title] => 'Write combining buffer that supports snoop request' [patent_app_type] => B1 [patent_app_number] => 09/309726 [patent_app_country] => US [patent_app_date] => 1999-05-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5206 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 48 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/366/06366984.pdf [firstpage_image] =>[orig_patent_app_number] => 09309726 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1557320 [patent_doc_number] => 06349375 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-02-19 [patent_title] => 'Compression of data in read only storage and embedded systems' [patent_app_type] => B1 [patent_app_number] => 09/309061 [patent_app_country] => US [patent_app_date] => 1999-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 6099 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/349/06349375.pdf [firstpage_image] =>[orig_patent_app_number] => 09309061 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6908554 [patent_doc_number] => 20010011321 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-08-02 [patent_title] => 'INFORMATION STORAGE AND RETRIEVAL SYSTEM' [patent_app_type] => new [patent_app_number] => 09/254437 [patent_app_country] => US [patent_app_date] => 1999-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4415 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 303 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0011/20010011321.pdf [firstpage_image] =>[orig_patent_app_number] => 09254437 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4391623 [patent_doc_number] => 06289420 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-11 [patent_title] => 'System and method for increasing the snoop bandwidth to cache tags in a multiport cache memory subsystem' [patent_app_type] => 1 [patent_app_number] => 9/306272 [patent_app_country] => US [patent_app_date] => 1999-05-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 4153 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/289/06289420.pdf [firstpage_image] =>[orig_patent_app_number] => 306272 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4239166 [patent_doc_number] => 06088781 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-07-11 [patent_title] => 'Stride instruction for fetching data separated by a stride amount' [patent_app_type] => 1 [patent_app_number] => 9/305936 [patent_app_country] => US [patent_app_date] => 1999-05-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 8770 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/088/06088781.pdf [firstpage_image] =>[orig_patent_app_number] => 305936 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1474989 [patent_doc_number] => 06408374 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-06-18 [patent_title] => 'Hashing method and apparatus' [patent_app_type] => B1 [patent_app_number] => 09/303461 [patent_app_country] => US [patent_app_date] => 1999-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 3507 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/408/06408374.pdf [firstpage_image] =>[orig_patent_app_number] => 09303461 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4423381 [patent_doc_number] => 06311255 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-30 [patent_title] => 'System and method for selectively restricting access to memory for bus attached unit IDs' [patent_app_type] => 1 [patent_app_number] => 9/302029 [patent_app_country] => US [patent_app_date] => 1999-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 5004 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/311/06311255.pdf [firstpage_image] =>[orig_patent_app_number] => 302029 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7638611 [patent_doc_number] => 06397310 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-28 [patent_title] => 'Method and apparatus for controlling write access to storage means for a digital data processing circuit' [patent_app_type] => B1 [patent_app_number] => 09/301999 [patent_app_country] => US [patent_app_date] => 1999-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 1352 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 32 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/397/06397310.pdf [firstpage_image] =>[orig_patent_app_number] => 09301999 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1557276 [patent_doc_number] => 06349370 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-02-19 [patent_title] => 'Multiple bus shared memory parallel processor and processing method' [patent_app_type] => B1 [patent_app_number] => 09/300461 [patent_app_country] => US [patent_app_date] => 1999-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 10256 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/349/06349370.pdf [firstpage_image] =>[orig_patent_app_number] => 09300461 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4349459 [patent_doc_number] => 06321290 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-11-20 [patent_title] => 'Program checking method, program checking apparatus, and computer-readable recording medium for recording target program checking program capable of reducing tracing interrupt time' [patent_app_type] => 1 [patent_app_number] => 9/300685 [patent_app_country] => US [patent_app_date] => 1999-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 21 [patent_no_of_words] => 18284 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 207 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/321/06321290.pdf [firstpage_image] =>[orig_patent_app_number] => 300685 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4298575 [patent_doc_number] => 06282614 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-28 [patent_title] => 'Apparatus and method for reducing the power consumption of a microprocessor with multiple levels of caches' [patent_app_type] => 1 [patent_app_number] => 9/292541 [patent_app_country] => US [patent_app_date] => 1999-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 10 [patent_no_of_words] => 4637 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/282/06282614.pdf [firstpage_image] =>[orig_patent_app_number] => 292541 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6226721 [patent_doc_number] => 20020004877 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-01-10 [patent_title] => 'METHOD AND SYSTEM FOR UPDATING USER MEMORY IN EMULATOR SYSTEMS' [patent_app_type] => new [patent_app_number] => 09/291190 [patent_app_country] => US [patent_app_date] => 1999-04-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4217 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 36 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0004/20020004877.pdf [firstpage_image] =>[orig_patent_app_number] => 09291190 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4423399 [patent_doc_number] => 06311257 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-30 [patent_title] => 'Method and system for allocating memory for a command queue' [patent_app_type] => 1 [patent_app_number] => 9/290844 [patent_app_country] => US [patent_app_date] => 1999-04-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 3281 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/311/06311257.pdf [firstpage_image] =>[orig_patent_app_number] => 290844 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1592321 [patent_doc_number] => 06360301 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-03-19 [patent_title] => 'Coherency protocol for computer cache' [patent_app_type] => B1 [patent_app_number] => 09/290430 [patent_app_country] => US [patent_app_date] => 1999-04-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2411 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/360/06360301.pdf [firstpage_image] =>[orig_patent_app_number] => 09290430 [rel_patent_id] =>[rel_patent_doc_number] =>)