Search

Than Vinh Nguyen

Examiner (ID: 3446, Phone: (571)272-4198 , Office: P/2138 )

Most Active Art Unit
2138
Art Unit(s)
2188, 2138, 2187, 2787, 2759, 2309, 2751
Total Applications
1861
Issued Applications
1652
Pending Applications
79
Abandoned Applications
148

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1495313 [patent_doc_number] => 06418511 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-07-09 [patent_title] => 'Large capacity data storage systems using redundant buses' [patent_app_type] => B1 [patent_app_number] => 09/222645 [patent_app_country] => US [patent_app_date] => 1998-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 6668 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/418/06418511.pdf [firstpage_image] =>[orig_patent_app_number] => 09222645 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/222645
Large capacity data storage systems using redundant buses Dec 29, 1998 Issued
Array ( [id] => 4280873 [patent_doc_number] => 06260119 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-10 [patent_title] => 'Memory cache management for isochronous memory access' [patent_app_type] => 1 [patent_app_number] => 9/221832 [patent_app_country] => US [patent_app_date] => 1998-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3623 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/260/06260119.pdf [firstpage_image] =>[orig_patent_app_number] => 221832 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/221832
Memory cache management for isochronous memory access Dec 28, 1998 Issued
Array ( [id] => 1553780 [patent_doc_number] => 06347362 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-02-12 [patent_title] => 'Flexible event monitoring counters in multi-node processor systems and process of operating the same' [patent_app_type] => B1 [patent_app_number] => 09/221577 [patent_app_country] => US [patent_app_date] => 1998-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 18 [patent_no_of_words] => 6677 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/347/06347362.pdf [firstpage_image] =>[orig_patent_app_number] => 09221577 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/221577
Flexible event monitoring counters in multi-node processor systems and process of operating the same Dec 28, 1998 Issued
Array ( [id] => 4337010 [patent_doc_number] => 06249838 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-19 [patent_title] => 'Physical medium information in file system header' [patent_app_type] => 1 [patent_app_number] => 9/221035 [patent_app_country] => US [patent_app_date] => 1998-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 6123 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/249/06249838.pdf [firstpage_image] =>[orig_patent_app_number] => 221035 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/221035
Physical medium information in file system header Dec 27, 1998 Issued
Array ( [id] => 1434036 [patent_doc_number] => 06341326 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-01-22 [patent_title] => 'Method and apparatus for data capture using latches, delays, parallelism, and synchronization' [patent_app_type] => B1 [patent_app_number] => 09/221229 [patent_app_country] => US [patent_app_date] => 1998-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1707 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/341/06341326.pdf [firstpage_image] =>[orig_patent_app_number] => 09221229 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/221229
Method and apparatus for data capture using latches, delays, parallelism, and synchronization Dec 22, 1998 Issued
09/218834 EFFICIENTLY, LOCALLY ADAPTIVE DATA REDUCTION METHOD AND APPARATUS Dec 21, 1998 Abandoned
Array ( [id] => 4208708 [patent_doc_number] => 06154807 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-28 [patent_title] => 'Memory system performing fast access to a memory location by omitting the transfer of a redundant address' [patent_app_type] => 1 [patent_app_number] => 9/188902 [patent_app_country] => US [patent_app_date] => 1998-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4941 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 211 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/154/06154807.pdf [firstpage_image] =>[orig_patent_app_number] => 188902 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/188902
Memory system performing fast access to a memory location by omitting the transfer of a redundant address Nov 9, 1998 Issued
Array ( [id] => 4366261 [patent_doc_number] => 06286087 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-04 [patent_title] => 'Method, apparatus, medium for storing and controlling accessibility to a removable medium' [patent_app_type] => 1 [patent_app_number] => 9/183607 [patent_app_country] => US [patent_app_date] => 1998-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 32 [patent_figures_cnt] => 40 [patent_no_of_words] => 14372 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/286/06286087.pdf [firstpage_image] =>[orig_patent_app_number] => 183607 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/183607
Method, apparatus, medium for storing and controlling accessibility to a removable medium Oct 29, 1998 Issued
Array ( [id] => 4171533 [patent_doc_number] => 06125430 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-26 [patent_title] => 'Virtual memory allocation in a virtual address space having an inaccessible gap' [patent_app_type] => 1 [patent_app_number] => 9/183677 [patent_app_country] => US [patent_app_date] => 1998-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 32 [patent_no_of_words] => 28725 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 214 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/125/06125430.pdf [firstpage_image] =>[orig_patent_app_number] => 183677 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/183677
Virtual memory allocation in a virtual address space having an inaccessible gap Oct 29, 1998 Issued
Array ( [id] => 6899285 [patent_doc_number] => 20010047450 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-11-29 [patent_title] => 'HIGH BANDWIDTH MEMORY INTERFACE' [patent_app_type] => new [patent_app_number] => 09/182494 [patent_app_country] => US [patent_app_date] => 1998-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 10155 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0047/20010047450.pdf [firstpage_image] =>[orig_patent_app_number] => 09182494 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/182494
High bandwidth memory interface Oct 29, 1998 Issued
Array ( [id] => 4422447 [patent_doc_number] => 06272599 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-07 [patent_title] => 'Cache structure and method for improving worst case execution time' [patent_app_type] => 1 [patent_app_number] => 9/183345 [patent_app_country] => US [patent_app_date] => 1998-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 1572 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/272/06272599.pdf [firstpage_image] =>[orig_patent_app_number] => 183345 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/183345
Cache structure and method for improving worst case execution time Oct 29, 1998 Issued
Array ( [id] => 4349888 [patent_doc_number] => 06321320 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-11-20 [patent_title] => 'Flexible and programmable BIST engine for on-chip memory array testing and characterization' [patent_app_type] => 1 [patent_app_number] => 9/183536 [patent_app_country] => US [patent_app_date] => 1998-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 6454 [patent_no_of_claims] => 92 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/321/06321320.pdf [firstpage_image] =>[orig_patent_app_number] => 183536 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/183536
Flexible and programmable BIST engine for on-chip memory array testing and characterization Oct 29, 1998 Issued
Array ( [id] => 4422116 [patent_doc_number] => 06233652 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-15 [patent_title] => 'Translation lookaside buffer for multiple page sizes' [patent_app_type] => 1 [patent_app_number] => 9/183685 [patent_app_country] => US [patent_app_date] => 1998-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 19 [patent_no_of_words] => 8142 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/233/06233652.pdf [firstpage_image] =>[orig_patent_app_number] => 183685 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/183685
Translation lookaside buffer for multiple page sizes Oct 29, 1998 Issued
Array ( [id] => 4422345 [patent_doc_number] => 06233669 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-15 [patent_title] => 'Memory address generator capable of row-major and column-major sweeps' [patent_app_type] => 1 [patent_app_number] => 9/183172 [patent_app_country] => US [patent_app_date] => 1998-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 16 [patent_no_of_words] => 8154 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/233/06233669.pdf [firstpage_image] =>[orig_patent_app_number] => 183172 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/183172
Memory address generator capable of row-major and column-major sweeps Oct 29, 1998 Issued
Array ( [id] => 1452320 [patent_doc_number] => 06370629 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-09 [patent_title] => 'Controlling access to stored information based on geographical location and date and time' [patent_app_type] => B1 [patent_app_number] => 09/182342 [patent_app_country] => US [patent_app_date] => 1998-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3533 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/370/06370629.pdf [firstpage_image] =>[orig_patent_app_number] => 09182342 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/182342
Controlling access to stored information based on geographical location and date and time Oct 28, 1998 Issued
Array ( [id] => 1214409 [patent_doc_number] => 06715049 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-03-30 [patent_title] => 'Microcomputer and information processing system' [patent_app_type] => B1 [patent_app_number] => 09/162999 [patent_app_country] => US [patent_app_date] => 1998-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 3665 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/715/06715049.pdf [firstpage_image] =>[orig_patent_app_number] => 09162999 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/162999
Microcomputer and information processing system Sep 29, 1998 Issued
Array ( [id] => 4270290 [patent_doc_number] => 06223263 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-24 [patent_title] => 'Method and apparatus for locking and unlocking a memory region' [patent_app_type] => 1 [patent_app_number] => 9/150518 [patent_app_country] => US [patent_app_date] => 1998-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 10 [patent_no_of_words] => 4486 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/223/06223263.pdf [firstpage_image] =>[orig_patent_app_number] => 150518 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/150518
Method and apparatus for locking and unlocking a memory region Sep 8, 1998 Issued
Array ( [id] => 4325397 [patent_doc_number] => 06253287 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-26 [patent_title] => 'Using three-dimensional storage to make variable-length instructions appear uniform in two dimensions' [patent_app_type] => 1 [patent_app_number] => 9/150310 [patent_app_country] => US [patent_app_date] => 1998-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 11 [patent_no_of_words] => 6856 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/253/06253287.pdf [firstpage_image] =>[orig_patent_app_number] => 150310 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/150310
Using three-dimensional storage to make variable-length instructions appear uniform in two dimensions Sep 8, 1998 Issued
Array ( [id] => 4424724 [patent_doc_number] => 06230237 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-08 [patent_title] => 'Content addressable memory with an internally-timed write operation' [patent_app_type] => 1 [patent_app_number] => 9/150513 [patent_app_country] => US [patent_app_date] => 1998-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2933 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/230/06230237.pdf [firstpage_image] =>[orig_patent_app_number] => 150513 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/150513
Content addressable memory with an internally-timed write operation Sep 8, 1998 Issued
Array ( [id] => 4424118 [patent_doc_number] => 06301642 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-09 [patent_title] => 'Shared memory bus arbitration system to improve access speed when accessing the same address set' [patent_app_type] => 1 [patent_app_number] => 9/149272 [patent_app_country] => US [patent_app_date] => 1998-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 5710 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/301/06301642.pdf [firstpage_image] =>[orig_patent_app_number] => 149272 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/149272
Shared memory bus arbitration system to improve access speed when accessing the same address set Sep 7, 1998 Issued
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