Search

Than Vinh Nguyen

Examiner (ID: 3446, Phone: (571)272-4198 , Office: P/2138 )

Most Active Art Unit
2138
Art Unit(s)
2188, 2138, 2187, 2787, 2759, 2309, 2751
Total Applications
1861
Issued Applications
1652
Pending Applications
79
Abandoned Applications
148

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4151685 [patent_doc_number] => 06035372 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-03-07 [patent_title] => 'Dynamic RAM in a microprocessor system' [patent_app_type] => 1 [patent_app_number] => 8/817875 [patent_app_country] => US [patent_app_date] => 1998-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 1959 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/035/06035372.pdf [firstpage_image] =>[orig_patent_app_number] => 817875 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/817875
Dynamic RAM in a microprocessor system Apr 22, 1998 Issued
Array ( [id] => 4269066 [patent_doc_number] => 06138208 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-24 [patent_title] => 'Multiple level cache memory with overlapped L1 and L2 memory access' [patent_app_type] => 1 [patent_app_number] => 9/059000 [patent_app_country] => US [patent_app_date] => 1998-04-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2598 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/138/06138208.pdf [firstpage_image] =>[orig_patent_app_number] => 059000 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/059000
Multiple level cache memory with overlapped L1 and L2 memory access Apr 12, 1998 Issued
Array ( [id] => 1602284 [patent_doc_number] => 06493816 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-12-10 [patent_title] => 'Method and apparatus for encapsulating address translation for shared persistent virtual storage' [patent_app_type] => B1 [patent_app_number] => 09/050831 [patent_app_country] => US [patent_app_date] => 1998-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 11999 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/493/06493816.pdf [firstpage_image] =>[orig_patent_app_number] => 09050831 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/050831
Method and apparatus for encapsulating address translation for shared persistent virtual storage Mar 29, 1998 Issued
Array ( [id] => 4279734 [patent_doc_number] => 06205515 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-20 [patent_title] => 'Column redundancy circuitry with reduced time delay' [patent_app_type] => 1 [patent_app_number] => 9/042893 [patent_app_country] => US [patent_app_date] => 1998-03-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 2665 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 291 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/205/06205515.pdf [firstpage_image] =>[orig_patent_app_number] => 042893 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/042893
Column redundancy circuitry with reduced time delay Mar 15, 1998 Issued
Array ( [id] => 4203940 [patent_doc_number] => 06151656 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-21 [patent_title] => 'Memory apparatus and method for controlling memory access based on memory address directivity' [patent_app_type] => 1 [patent_app_number] => 9/031543 [patent_app_country] => US [patent_app_date] => 1998-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 6291 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/151/06151656.pdf [firstpage_image] =>[orig_patent_app_number] => 031543 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/031543
Memory apparatus and method for controlling memory access based on memory address directivity Feb 26, 1998 Issued
Array ( [id] => 4323995 [patent_doc_number] => 06189083 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-13 [patent_title] => 'Method and apparatus for accessing a cache memory utilization distingushing bit RAMs' [patent_app_type] => 1 [patent_app_number] => 9/030797 [patent_app_country] => US [patent_app_date] => 1998-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 18 [patent_no_of_words] => 12256 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/189/06189083.pdf [firstpage_image] =>[orig_patent_app_number] => 030797 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/030797
Method and apparatus for accessing a cache memory utilization distingushing bit RAMs Feb 25, 1998 Issued
Array ( [id] => 4238993 [patent_doc_number] => 06088770 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-07-11 [patent_title] => 'Shared memory multiprocessor performing cache coherency' [patent_app_type] => 1 [patent_app_number] => 9/030957 [patent_app_country] => US [patent_app_date] => 1998-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 20 [patent_no_of_words] => 11260 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/088/06088770.pdf [firstpage_image] =>[orig_patent_app_number] => 030957 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/030957
Shared memory multiprocessor performing cache coherency Feb 25, 1998 Issued
Array ( [id] => 4270348 [patent_doc_number] => 06223267 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-24 [patent_title] => 'Dynamically allocable RAM disk' [patent_app_type] => 1 [patent_app_number] => 9/031504 [patent_app_country] => US [patent_app_date] => 1998-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1408 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/223/06223267.pdf [firstpage_image] =>[orig_patent_app_number] => 031504 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/031504
Dynamically allocable RAM disk Feb 25, 1998 Issued
Array ( [id] => 4200024 [patent_doc_number] => 06021475 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-01 [patent_title] => 'Method and apparatus for polling and selecting any paired device in any drawer' [patent_app_type] => 1 [patent_app_number] => 9/026366 [patent_app_country] => US [patent_app_date] => 1998-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 9251 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 190 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/021/06021475.pdf [firstpage_image] =>[orig_patent_app_number] => 026366 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/026366
Method and apparatus for polling and selecting any paired device in any drawer Feb 18, 1998 Issued
Array ( [id] => 1552894 [patent_doc_number] => 06446173 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-09-03 [patent_title] => 'Memory controller in a multi-port bridge for a local area network' [patent_app_type] => B1 [patent_app_number] => 09/025355 [patent_app_country] => US [patent_app_date] => 1998-02-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 15612 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/446/06446173.pdf [firstpage_image] =>[orig_patent_app_number] => 09025355 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/025355
Memory controller in a multi-port bridge for a local area network Feb 17, 1998 Issued
Array ( [id] => 4423403 [patent_doc_number] => 06311258 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-30 [patent_title] => 'Data buffer apparatus and method for storing graphical data using data encoders and decoders' [patent_app_type] => 1 [patent_app_number] => 9/025843 [patent_app_country] => US [patent_app_date] => 1998-02-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 135 [patent_figures_cnt] => 167 [patent_no_of_words] => 69119 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 250 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/311/06311258.pdf [firstpage_image] =>[orig_patent_app_number] => 025843 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/025843
Data buffer apparatus and method for storing graphical data using data encoders and decoders Feb 17, 1998 Issued
Array ( [id] => 3955507 [patent_doc_number] => 05940875 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-17 [patent_title] => 'Address pattern generator for burst address access of an SDRAM' [patent_app_type] => 1 [patent_app_number] => 9/016710 [patent_app_country] => US [patent_app_date] => 1998-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 3713 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 194 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/940/05940875.pdf [firstpage_image] =>[orig_patent_app_number] => 016710 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/016710
Address pattern generator for burst address access of an SDRAM Jan 29, 1998 Issued
Array ( [id] => 4138830 [patent_doc_number] => 06073217 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-06-06 [patent_title] => 'Method for detecting updates to instructions which are within an instruction processing pipeline of a microprocessor' [patent_app_type] => 1 [patent_app_number] => 9/015087 [patent_app_country] => US [patent_app_date] => 1998-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 7191 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/073/06073217.pdf [firstpage_image] =>[orig_patent_app_number] => 015087 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/015087
Method for detecting updates to instructions which are within an instruction processing pipeline of a microprocessor Jan 28, 1998 Issued
Array ( [id] => 4109991 [patent_doc_number] => 06134634 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-17 [patent_title] => 'Method and apparatus for preemptive cache write-back' [patent_app_type] => 1 [patent_app_number] => 8/994730 [patent_app_country] => US [patent_app_date] => 1997-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 8997 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/134/06134634.pdf [firstpage_image] =>[orig_patent_app_number] => 994730 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/994730
Method and apparatus for preemptive cache write-back Dec 18, 1997 Issued
Array ( [id] => 4252320 [patent_doc_number] => 06076134 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-06-13 [patent_title] => 'Memory patching device' [patent_app_type] => 1 [patent_app_number] => 8/982314 [patent_app_country] => US [patent_app_date] => 1997-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 3237 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/076/06076134.pdf [firstpage_image] =>[orig_patent_app_number] => 982314 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/982314
Memory patching device Nov 30, 1997 Issued
Array ( [id] => 4388059 [patent_doc_number] => 06275896 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-14 [patent_title] => 'Data transfer apparatus and method of the same and data input and output controlling apparatus and method of same' [patent_app_type] => 1 [patent_app_number] => 8/979755 [patent_app_country] => US [patent_app_date] => 1997-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 4545 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 233 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/275/06275896.pdf [firstpage_image] =>[orig_patent_app_number] => 979755 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/979755
Data transfer apparatus and method of the same and data input and output controlling apparatus and method of same Nov 25, 1997 Issued
Array ( [id] => 4333182 [patent_doc_number] => 06332178 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-12-18 [patent_title] => 'Method for estimating statistics of properties of memory system transactions' [patent_app_type] => 1 [patent_app_number] => 8/980165 [patent_app_country] => US [patent_app_date] => 1997-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7520 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 13 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/332/06332178.pdf [firstpage_image] =>[orig_patent_app_number] => 980165 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/980165
Method for estimating statistics of properties of memory system transactions Nov 25, 1997 Issued
Array ( [id] => 4269200 [patent_doc_number] => 06138217 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-24 [patent_title] => 'Method and apparatus for cache coherency in an interconnecting network' [patent_app_type] => 1 [patent_app_number] => 8/976236 [patent_app_country] => US [patent_app_date] => 1997-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 6380 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 12 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/138/06138217.pdf [firstpage_image] =>[orig_patent_app_number] => 976236 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/976236
Method and apparatus for cache coherency in an interconnecting network Nov 20, 1997 Issued
Array ( [id] => 4211410 [patent_doc_number] => 06044442 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-03-28 [patent_title] => 'External partitioning of an automated data storage library into multiple virtual libraries for access by a plurality of hosts' [patent_app_type] => 1 [patent_app_number] => 8/976050 [patent_app_country] => US [patent_app_date] => 1997-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 5949 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 204 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/044/06044442.pdf [firstpage_image] =>[orig_patent_app_number] => 976050 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/976050
External partitioning of an automated data storage library into multiple virtual libraries for access by a plurality of hosts Nov 20, 1997 Issued
Array ( [id] => 4092437 [patent_doc_number] => 05966737 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-10-12 [patent_title] => 'Apparatus and method for serialized set prediction' [patent_app_type] => 1 [patent_app_number] => 8/971630 [patent_app_country] => US [patent_app_date] => 1997-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5098 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/966/05966737.pdf [firstpage_image] =>[orig_patent_app_number] => 971630 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/971630
Apparatus and method for serialized set prediction Nov 16, 1997 Issued
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