Than Vinh Nguyen

Array ( [id] => 4167226 [patent_doc_number] => 06065098 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-16 [patent_title] => 'Method for maintaining multi-level cache coherency in a processor with non-inclusive caches and processor implementing the same' [patent_app_type] => 1 [patent_app_number] => 8/932826 [patent_app_country] => US [patent_app_date] => 1997-09-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 8 [patent_no_of_words] => 3858 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/065/06065098.pdf [firstpage_image] =>[orig_patent_app_number] => 932826 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4145426 [patent_doc_number] => 06034965 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-03-07 [patent_title] => 'Multi-stream associative memory architecture for computer telephony' [patent_app_type] => 1 [patent_app_number] => 8/931710 [patent_app_country] => US [patent_app_date] => 1997-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 2627 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/034/06034965.pdf [firstpage_image] =>[orig_patent_app_number] => 931710 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4240151 [patent_doc_number] => 06012130 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-01-04 [patent_title] => 'Method and apparatus for automated disk drive upgrades' [patent_app_type] => 1 [patent_app_number] => 8/923662 [patent_app_country] => US [patent_app_date] => 1997-09-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 5480 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/012/06012130.pdf [firstpage_image] =>[orig_patent_app_number] => 923662 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4252460 [patent_doc_number] => 06076143 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-06-13 [patent_title] => 'Method and apparatus for managing the physical storage locations for blocks of information in a storage system to increase system performance' [patent_app_type] => 1 [patent_app_number] => 8/922227 [patent_app_country] => US [patent_app_date] => 1997-09-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 15 [patent_no_of_words] => 14773 [patent_no_of_claims] => 42 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 237 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/076/06076143.pdf [firstpage_image] =>[orig_patent_app_number] => 922227 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4279940 [patent_doc_number] => 06205528 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-20 [patent_title] => 'User specifiable allocation of memory for processes in a multiprocessor computer having a non-uniform memory architecture' [patent_app_type] => 1 [patent_app_number] => 8/920672 [patent_app_country] => US [patent_app_date] => 1997-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5091 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/205/06205528.pdf [firstpage_image] =>[orig_patent_app_number] => 920672 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4199125 [patent_doc_number] => 06038645 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-03-14 [patent_title] => 'Microprocessor circuits, systems, and methods using a combined writeback queue and victim cache' [patent_app_type] => 1 [patent_app_number] => 8/919732 [patent_app_country] => US [patent_app_date] => 1997-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 8958 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/038/06038645.pdf [firstpage_image] =>[orig_patent_app_number] => 919732 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3960482 [patent_doc_number] => 05930833 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-07-27 [patent_title] => 'Logical cache memory storing logical and physical address information for resolving synonym problems' [patent_app_type] => 1 [patent_app_number] => 8/924551 [patent_app_country] => US [patent_app_date] => 1997-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 16 [patent_no_of_words] => 7981 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/930/05930833.pdf [firstpage_image] =>[orig_patent_app_number] => 924551 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3944397 [patent_doc_number] => 05946713 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-31 [patent_title] => 'Memory attribute palette' [patent_app_type] => 1 [patent_app_number] => 8/914578 [patent_app_country] => US [patent_app_date] => 1997-08-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4487 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/946/05946713.pdf [firstpage_image] =>[orig_patent_app_number] => 914578 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4256893 [patent_doc_number] => 06081869 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-06-27 [patent_title] => 'Bit-field peripheral' [patent_app_type] => 1 [patent_app_number] => 8/907066 [patent_app_country] => US [patent_app_date] => 1997-08-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 3324 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/081/06081869.pdf [firstpage_image] =>[orig_patent_app_number] => 907066 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4007026 [patent_doc_number] => 05960466 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-28 [patent_title] => 'Computer address translation using fast address generator during a segmentation operation performed on a virtual address' [patent_app_type] => 1 [patent_app_number] => 8/905410 [patent_app_country] => US [patent_app_date] => 1997-08-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 7197 [patent_no_of_claims] => 43 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/960/05960466.pdf [firstpage_image] =>[orig_patent_app_number] => 905410 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4427310 [patent_doc_number] => 06226733 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-01 [patent_title] => 'Address translation mechanism and method in a computer system' [patent_app_type] => 1 [patent_app_number] => 8/905356 [patent_app_country] => US [patent_app_date] => 1997-08-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 7197 [patent_no_of_claims] => 74 [patent_no_of_ind_claims] => 17 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/226/06226733.pdf [firstpage_image] =>[orig_patent_app_number] => 905356 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4259674 [patent_doc_number] => 06092146 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-07-18 [patent_title] => 'Dynamically configurable memory adapter using electronic presence detects' [patent_app_type] => 1 [patent_app_number] => 8/904187 [patent_app_country] => US [patent_app_date] => 1997-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 4232 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/092/06092146.pdf [firstpage_image] =>[orig_patent_app_number] => 904187 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3996125 [patent_doc_number] => 05918253 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-06-29 [patent_title] => 'Memory address generator' [patent_app_type] => 1 [patent_app_number] => 8/904045 [patent_app_country] => US [patent_app_date] => 1997-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4124 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/918/05918253.pdf [firstpage_image] =>[orig_patent_app_number] => 904045 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4057407 [patent_doc_number] => 05996050 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-30 [patent_title] => 'Cache coherency detection in a bus bridge verification system' [patent_app_type] => 1 [patent_app_number] => 8/904434 [patent_app_country] => US [patent_app_date] => 1997-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 13 [patent_no_of_words] => 9381 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/996/05996050.pdf [firstpage_image] =>[orig_patent_app_number] => 904434 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3954749 [patent_doc_number] => 05873126 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-02-16 [patent_title] => 'Memory array based data reorganizer' [patent_app_type] => 1 [patent_app_number] => 8/902409 [patent_app_country] => US [patent_app_date] => 1997-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2342 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 185 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/873/05873126.pdf [firstpage_image] =>[orig_patent_app_number] => 902409 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3932836 [patent_doc_number] => 06003115 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-12-14 [patent_title] => 'Method and apparatus for predictive loading of a cache' [patent_app_type] => 1 [patent_app_number] => 8/902441 [patent_app_country] => US [patent_app_date] => 1997-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 5985 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/003/06003115.pdf [firstpage_image] =>[orig_patent_app_number] => 902441 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4026673 [patent_doc_number] => 05890186 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-03-30 [patent_title] => 'Memory circuit with built-in cache memory' [patent_app_type] => 1 [patent_app_number] => 8/895863 [patent_app_country] => US [patent_app_date] => 1997-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 33 [patent_no_of_words] => 8281 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 278 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/890/05890186.pdf [firstpage_image] =>[orig_patent_app_number] => 895863 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4099970 [patent_doc_number] => 06055612 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-04-25 [patent_title] => 'Incremental garbage collector with decommit barrier' [patent_app_type] => 1 [patent_app_number] => 8/891687 [patent_app_country] => US [patent_app_date] => 1997-07-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4493 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 24 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/055/06055612.pdf [firstpage_image] =>[orig_patent_app_number] => 891687 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4138584 [patent_doc_number] => 06073205 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-06-06 [patent_title] => 'System and method of write posting in a universal serial bus system' [patent_app_type] => 1 [patent_app_number] => 8/891150 [patent_app_country] => US [patent_app_date] => 1997-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5296 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/073/06073205.pdf [firstpage_image] =>[orig_patent_app_number] => 891150 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4424566 [patent_doc_number] => 06266753 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-24 [patent_title] => 'Memory manager for multi-media apparatus and method therefor' [patent_app_type] => 1 [patent_app_number] => 8/890825 [patent_app_country] => US [patent_app_date] => 1997-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5654 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 12 [patent_words_short_claim] => 212 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/266/06266753.pdf [firstpage_image] =>[orig_patent_app_number] => 890825 [rel_patent_id] =>[rel_patent_doc_number] =>)